Embedded Systems 2002/2003 (c) Daniel Kästner.
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EPIC: IA64 - Intel Itanium
Block diagram of Intel Intanium.
Embedded Systems 2002/2003 (c) Daniel Kästner.
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IA-64 Architecture
• Support for
– branch prediction (minimize the cost of branches),
– predicated execution (remove branches),
– control speculation and data speculation (reduce memory
latency effects)
– cache hints (compiler prediction of spatial or temporal
locality of the memory area being accessed; can be used for
placement of cache lines in the cache hierarchy by the
processor)
• Register sets:
– 128 64-bit general purpose registers: GR0-GR127
– 128 80-bit floating-point registers: FR0-FR127
– 64 1-bit predicate registers: PR0-PR63
– 8 64-bit branch registers: BR0-BR7
– features: register stack and rotating registers
Embedded Systems 2002/2003 (c) Daniel Kästner.
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IA-64 Architecture
Embedded Systems 2002/2003 (c) Daniel Kästner.
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IA-64 Architecture
• Each IA-64 instruction is categorized into 6 types and may be executed
on one or more execution unit types.
• 4 functional unit categories:
– I unit (integer)
– F unit (floating-point)
– M unit (memory)
– B unit (branch)
• 6 microoperation categories:
– Integer ALU (A-type)
executed on M- or I units
– Non-ALU Integer (I-type)
executed on I units
– Memory (M-type)
executed on M units
– Floating-point (F-type)
executed on F units
– Branch (B-type)
executed on B units
– Extended (L/X-type)
executed on I- or B units
Embedded Systems 2002/2003 (c) Daniel Kästner.
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IA-64 Architecture
• The IA-64 defines 128-bit long instruction words (called
bundles) consisting of three 41-bit microoperations and a 5-bit
template field. Multiple bundles can be issued per clock cycle
(number is defined by implementation).
• Template field:
– helps decode and route instructions
– indicates the location of stops that mark the end of groups of
microoperations that can execute in parallel
• Dispersal: process of sending instructions to functional units.
instruction slot 1
t(5)
instruction slot 2
instruction slot 0
Emb