Memory Design Considerations
when Migrating to DDR3
Interfaces from DDR2
Raj Mahajan, MemCore Inc.
The emerging DDR3 memory standard will extend the performance range of DDR
memories considerably, while maintaining some amount of backwards compatibility with
the existing DDR2 memory standard. It is important to understand the similarities and
differences between the DDR3 standard and the existing DDR2 standard in order to get
the maximum benefit from the new standard while re-using as much as possible from any
previous DDR2 memory interface design. This paper will provide the reader with a
detailed understanding of the key design considerations when migrating to a DDR3
system interface from a DDR2 interface.
This paper will review the new DDR3 features and compare and contrast them to
previous features available in the DDR2 specification. One of the biggest changes is the
in Physical Layer (PHY) portion of the memory interface and these changes will be high-
lighted and illustrated with an example design of a high performance processor interface.
The areas where backwards compatibility should be maintained will also be illustrated
with an example design, showing how simple changes can provide significant benefits in
re-use and system flexibility.
Raj Mahajan has more than 10 years of experience architecting, designing, and verifying
memory access solutions for advanced ASICs for a variety of target markets. He started
his career at Intel Corp, where he architected and designed advanced render cache
controllers that shipped hundreds of millions of units in several generations of graphics-
enabled PC chipsets. Following that he held a lead design position at 2Wire, Inc., a
successful start-up addressing the residential broadband access market, where he led the
integration and verification of their flagship SoC, which shipped first silicon. At Ingot