DMA Hints on IA64/PARISC
Optimizing DMA performance for HP Chip sets
Modern IO subsystems implement complex
DMA transaction parameters, called DMA
hints, which are not explicitly supported by
the Linux DMA API. This paper investigates
benefits of using non-default DMA hints and
thus whether such hints should be abstracted
into the DMA API. My conclusion is the im-
plementation (ZX1) investigated does not war-
rant changing the DMA API. Other implemen-
tations need to be compared before proposing
HP PA-RISC (Astro/Elroy) and IA64 IO
Controllers (ZX1) both support several types of
DMA hints and both are commercially avail-
able. My primary interest was the ability to
prefetch cache lines for PCI devices. The ben-
efit is same as for CPU: bring the data closer
to the consumer. But to my surprise, cache line
prefetching is not the most important hint since
default prefetching works well for all devices.
Relaxing the PCI ordering rules turns out to
be more important since firmware can’t know
when it’s safe to do so.
Updated versions of this paper will be avail-
able from http://iou.parisc-linux.
DMA performance seems like such an obvious
thing. Drivers just need to tell the device where
to fetch something from memory, poke it, and
life is good. Unfortunately, those days are over.
Modern SMP servers require multiple levels of
bridges in order to support PCI-X Bandwidth
(peak burst rate 133MHz/64-bits). In order to
work well with CPUs and memory controllers,
IO Devices participate in the CPU Cache Co-
herency protocols. They also need to minimize
the number transactions used and use the ap-
propriate type of transaction in order to opti-
mally utilize available bandwidth.
Throughout this paper (and even in the title!)
I use the word Hint which implies an “infor-
mational only” parameter. This isn’t strictly
accurate. Some platforms depend on certain
parameters for correct operation. I.e.
rect results may occ