10-5 80386DX AND 80486
(32-BIT) MEMORY INTERFACE
80386DX and 80486 have 32-bit data buses and
therefore 4 banks of memory.
32-bit, 16-bit and 8-bit transfers are accomplished by
different combinations of the bank selection signals BE3,
BE2, BE1, BE0.
The Address bits A0 and A1 are used within the
microprocessor to generate these signals.
The high clock rates of these processors usually
require wait states for memory access.
10-6 PENTIUM MEMORY
z The Pentium, Pentium Pro, Pentium II
and III contain a 64-bit data bus.
Therefore, 8 decoders or 8 write strobes are
needed as well as 8 memory banks.
Generation of Write Strobes
The write strobes are obtained by combining the bank
enable signals (BEx) with the MWTC signal.
MWTC is generated by combining the M/IO and W/R
p.370-373 64-Bit Memory Interface
64-Bit Memory Interface (Cont'd)
In order to map previous memory into addr. space
Use a 16L8 to do the WR0 - WR7 decoding using MWTC
and BE0 - BE7.
See the text: p.369 Fig.10-35.
10-7 DYNAMIC RAM
Memory Architecture (1/4)
In order to build an N-word memory where each word is M bits wide
(typically 1, 4 or 8 bits), a straightforward approach is to stack
A word is selected by setting exactly
one of the select bits, Sx, high.
This approach works well for small memories
but has problems for large memories.
For example, to build a 1M word (where word
= 8 bits) memory, requires 1M select lines,
provided by some off-chip device.
This approach is not practical.
What can we do?
Add a decoder to solve the package problem:
This does not address the memory aspect ratio problem:
The memory is 128,000 time higher than wide (220/23) !
Besides the bizarre shape factor, the design is extremely slow
since the vertical wires are VERY long (delay is at least linear to
This reduces the number of
external address pins from
1M to 20.
Memory Architecture (2/4)
Memory Architecture (3/4)
The vertical and h