Abstract—The Elan5 is a single chip network processor
which acts as a host adapter for high speed network
protocols. It is capable of handling both 10Gb Ethernet,
and proprietary Quadrics protocols developed for ultra low
latency communication in High Performance Computing
applications. In order to provide flexibility in the choice of
protocols the device is implemented as an array of identical
RISC processors, which can be dedicated to tasks such as
input packet handling and host memory DMA handling.
Index Terms—10GbE, HPC, Ethernet, QsNet
INTRODUCTION
HE Elan5 Network processor marks a significant
departure from the preceding generations of high
speed Network Interface devices [1] in several aspects.
The device implements a standard-based protocol, IEEE
802.3ae [2] in addition to the ultra low latency protocols
developed for supercomputing applications. This choice
was dictated by the requirement to address wider markets
to offset the increasing development costs of the latest
generations of CMOS technology, while at the same time
maintaining a performance advantage when used in
supercomputer class systems.
The requirement to implement multiple protocols
necessitates a much greater degree of programmability in
the underlying architecture than in preceding generations
of device. For example in Elan4 the only form of DMA
supported is a simple RDMA operation in which a
contiguous memory block is transferred between nodes.
By implementing the DMA function in a processor
instead of a dedicated state machine it is possible to
implement more complex functions, such as Ethernet
RDMA and various forms of scatter gather operation.
The Elan5’s processing power is provided by a pool of
Packet Processing Engines (PPEs) designed specifically
to support the high speed streaming of data. Multiple
PPEs are provided so as to maximize the packet rate and
minimize the packet size necessary to saturate link
bandwidth. The PPEs share a multi bank memory system
on the chip. Commu