180
C H A P T E R
5
T H E C M O S I N V E R T E R
Quantification of integrity, performance, and energy metrics of an inverter
Optimization of an inverter design
5.1 Exercises and Design Problems
5.2 The Static CMOS Inverter — An Intuitive
Perspective
5.3 Evaluating the Robustness of the CMOS
Inverter: The Static Behavior
5.3.1 Switching Threshold
5.3.2 Noise Margins
5.3.3 Robustness Revisited
5.4 Performance of CMOS Inverter: The Dynamic
Behavior
5.4.1 Computing the Capacitances
5.4.2 Propagation Delay: First-Order
Analysis
5.4.3 Propagation Delay from a Design
Perspective
5.5
Power, Energy, and Energy-Delay
5.5.1 Dynamic Power Consumption
5.5.2 Static Consumption
5.5.3 Putting It All Together
5.5.4 Analyzing Power Consumption Using
SPICE
5.6 Perspective: Technology Scaling and its
Impact on the Inverter Metrics
Section 5.1
Exercises and Design Problems
181
5.1 Exercises and Design Problems
1.
[M, SPICE, 3.3.2] The layout of a static CMOS inverter is given in Figure 5.1. (λ = 0.125
µm).
a. Determine the sizes of the NMOS and PMOS transistors.
Solution
The sizes are wn=1.0µm, ln=0.25µm, wp=0.5µm, and lp=0.25 µm.
b. Plot the VTC (using HSPICE) and derive its parameters (VOH, VOL, VM, VIH, and VIL).
Solution
The inverter VTC is shown below. For a static CMOS inverter with a supply voltage of
2.5 V, VOH =2.5 V and VOL=0 V. In order to calculate Vm , note from the VTC that the value is
between 0.8 V and 0.9 V. Therefore, the NMOS is saturated and the PMOS is velocity satu-
rated. Let Vin=Vout=Vm and set the currents equal to obtain the following equation:
(kn/2)(VGS-VTN)
2(1+λVDS)=kpVDSAT[(VGS-VTP)-(VDSAT/2)](1+λVDS)
Substitute the appropriate values and solve numerically to find Vm=0.883 V.
Use the VTC data to solve for VIL and VIH numerically. The result is that VIH=0.97 V and
VIL=0.56 V.
c. Is the VTC affected when the output of the gates is connected to the inputs of 4 similar
gates?
Solution
No. CMOS gates are a purely capacitive load so the DC circuit characteristics are not
affected.
0
0.5
1
1.5
2
2.5
−0.5
0
0.