Clocking Circuits for a 16Gb/s Memory Interface
Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun,
TJ Chin, Jie Shen, Rich Perego, and Ken Chang
Rambus Inc. 4440 El Camino Real, Los Altos, CA 94022, USA
Abstract - 8GHz clocking circuits for a 16Gb/s/pin asymmetric
memory interface [1] are described. A combination of an LC-
PLL and a ring-PLL achieves improved jitter performance for
multiple phase outputs with a wide frequency range. A direct
phase mixer and a digitally controlled duty-cycle corrector
(DCC) are time-multiplexed between transmitter (TX) and
receiver (RX), thereby reducing area and power. The prototype
chip implemented in a 65nm CMOS technology has measured
734fs RJ (rms) at the TX output when operating at 16Gb/s.
I. Introduction
Driven by today’s advances in personal computing, game
consoles, mobile phones, and HDTV, the demand for high
bandwidth memory interfaces has been steadily growing. As
the performance demands of memory interfaces increase,
clock generation and distribution techniques are among the
most important design considerations [2]. To meet the market
requirements, clocking circuits must achieve both low jitter
and low power at an increasingly higher data rate.
In this paper, we present a high-performance clocking
architecture featuring dual-loop PLLs on the controller side of
an asymmetric memory interface [1]. An LC oscillator based
PLL produces a low jitter high frequency clock as the
reference clock of a ring oscillator based PLL. The ring-PLL
then generates quadrature phase outputs, which drive phase
mixers for clock phase adjustments. As a consequence, the
overall architecture achieves improved jitter performance for
multiple phase outputs with a wide frequency range.
To simplify the interface circuitry of the associated DRAM
devices, the controller interface must ensure a ~50% duty-
cycle with 360-degree phase adjustment at both TX and RX
circuits. The phase adjustment and duty-cycle adjustment are
achieved by