HIGH SPEED SQUARER
Chandra Mohan Umapathy
Senior IC Design Engineer
Celstream Technologies Private Limited
Prestige Blue Chip, Block II
#9, Hosur Road, Bangalore: 29
Abstract: This paper proposes a novel architecture for modular, scalable &
reusable hybrid squaring circuit. Comparison is made between different
implementations of squaring circuit. The implementation results show a
significant improvement in performance in terms of area, power & timing.
The paper is organized as follows: the first section gives a brief
introduction of the different aspects & the motivation for the High Speed
Squarers. The second section introduces the proposed algorithm. The third
section explains the proposed architecture. The fourth section deals with the
comparison of the proposed architecture with the existing method & conclusion.
Key Words: Squarer, Squaring Circuit, Multiplier, Low Power etc.
SECTION 1: Introduction:
Squaring is one of the frequently performed functions in most of the DSP
systems. Squaring is a special case of multiplication. Squaring circuit forms the
heart of the different DSP operations like Image Compression, Decoding,
Demodulation, Adaptive Filtering, Least Mean Squaring etc.
Traditionally, squaring was performed using multiplier itself. As the
applications evolved & the demand for the high speed processing increased,
special attention was given for squaring function & dedicated squarers were
proposed & implemented.
Initially, squaring was performed using Look Up Table approach if
delay was primary concern, while trading of the area constraint. Major drawback
of the scheme was area penalty, which increases exponentially as the number of
input bits increases. Due to the cost & the interconnect delay this approach was
not most preferred implementation method till now. Recently, with the evolution
of VLSI Process Technology the above method of implementation is becoming
Recently, lot of research has been