LFSR Counter Implementation in CMOS VLSI
Doshi N. A., Dhobale S. B., and Kakade S. R.
Abstract—As chip manufacturing technology is suddenly on the
threshold of major evaluation, which shrinks chip in size and
performance, LFSR (Linear Feedback Shift Register) is implemented
in layout level which develops the low power consumption chip,
using recent CMOS, sub-micrometer layout tools. Thus LFSR
counter can be a new trend setter in cryptography and is also
beneficial as compared to GRAY & BINARY counter and variety of
This paper compares 3 architectures in terms of the hardware
implementation, CMOS layout and power consumption, using
Microwind CMOS layout tool. Thus it provides solution to a low
power architecture implementation of LFSR in CMOS VLSI.
level, LFSR, Pass
ITH advancements in large scale integration, millions
of transistors can be placed on a single chip for
implementation of complex circuitry. As a result of placing so
many transistors in such a small space, major problems of heat
dissipation and power consumption have come into the
picture. Research has been conducted to solve these problems.
Solutions have been proposed to decrease the power supply
voltage, switching frequency and capacitance of transistor 
LFSR is used in a variety of applications such as Built-in-self
test (BIST) , cryptography, error correction code and in
for generating pseudo-noise
sequences. In cryptography it is used to generate public and
private keys. Hence one of the low power architecture is
proposed in this paper.
Today LFSR’s are present in nearly every coding scheme as
they produce sequences with good statistical properties, and
they can be easily analyzed. Moreover they have a low-cost
realization in hardware.