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Bluespec IA-64 Modeling
Roland Wunderlich and James C. Hoe
Computer Architecture Lab (CALCM)
Carnegie Mellon University
Bluespec Workshop, January 2003, Slide 2
J. C. Hoe, CMU/ECE
Motivation
! Combining high-level description/synthesis
and FPGAs for rapid processor prototyping
an alternative to software simulation studies
! Allow direct evaluation of new mechanisms
- Functionality: a fast emulator that can run real
software but remains infinitely malleable
completeness, correctness, …..
- Implementation: a synthesized design gives hints
about feasibility, design complexity and
implementation cost
area,cycle time, power, …..
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Bluespec Workshop, January 2003, Slide 3
J. C. Hoe, CMU/ECE
Current Project
! Develop a high-level model of IA-64
microarchitectures
- concise and malleable
- detailed = executable and synthesizable
! Synthesize to FPGA
- to target XC2V6000 FPGA board in a P6 processor
slot
- to execute binaries natively on the FPGA
processor against a new PC environment
! Current Modeling Challenges
- processor complexity
- trade-off between µarch realism and design effort
Bluespec Workshop, January 2003, Slide 4
J. C. Hoe, CMU/ECE
Why Bluespec?
! Detailed
- nothing left to interpretation
- litmus test: can it be executed or synthesized
automatically?
! Concise
- compact and expressive
- natural correspondence to HW structures and
abstractions
!Maintainable
- easy to understand
- modular: composible and decomposible
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Bluespec Workshop, January 2003, Slide 5
J. C. Hoe, CMU/ECE
IA64 Modeling
Bluespec Workshop, January 2003, Slide 6
J. C. Hoe, CMU/ECE
Current IA64 Model
! Basic framework for a 6-wide Itanium datapath
- decoding rules for all user-level, non-FP instructions
- 2 br. unit, 2 mem/int unit, 4 integer unit
- bypassing for integer unit, scoreboarding for remaining
- currently supports execution of
alloc (register stack but no rotation, no spill engine)
mov (branch registers to general registers and vice versa)
cmp.*.unc (all relations, all immediate forms, compare to
zero)
add, adds, a