TEACHING CUSTOM AND AUTOMATED CELL DESIGN
DONALD W. BOULDIN, CHANDRA TAN and KAUSHIK J. PATEL
Electrical & Computer Engineering
University of Tennessee
Knoxville, TN 37996-2100
dbouldin@tennessee.edu
1. Introduction
Custom design and verification of leaf-cells for standard-height and bit-slice
libraries can be used to provide students with experience in performing these
physical level tasks manually. We describe a one-semester graduate course
[1] in which students compare their own custom layouts with automated results
in terms of area, delay and design time. The availability of valid automated
solutions provides the students with targets that serve as feasible bounds on
the layouts and also inspire competition between the student and the design
automation software. Projects are combined into TinyChips and submitted for
fabrication via MOSIS [2] for testing during the subsequent semester.
2. Design and Verification Flow
The Cadence Design Systems [3] custom integrated circuit design bundle was
selected to support the laboratory assignments in this course because it
provides students with an integrated flow for custom design and verification.
As shown in part of Figure 1, the designer begins by entering a hierarchical
schematic to specify the desired logic and the W/L of each transistor. The
resulting net-list is then simulated using detailed transistor models (Spectre).
ProGenesis [4] is an automatic leaf-cell generator. As shown in Figure 1,
ProGenesis accepts the same transistor-level net-list as Virtuoso (after a format
conversion). The tool also reads a process rule file so that it is cognizant of the
desired spacings and thus produces layout that is free of geometric design rule
errors. It can also read in a constraint file so that the layout can be compliant
with standard-height constraints for power and ground spacing as well as pin
locations. The resulting layout is then verified in the same manner as a
custom layout.
For bit-slice leaf-cells, a c