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Chapter 6
FET Biasing
Chapter 6 FET Biasing
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INTRODUCTION
The general relationships that can be applied to the dc analysis of all FET amplifiers
are
and
For JFETs and depletion-type MOSFETs, Shockley’s equation is applied to relate the
input and output quantities:
For enhancement-type MOSFETs, the following equation is applicable:
It is particularly important to realize that all of the equations above are for the
device only!. They do not change with each network configuration so long as the
device is in active region.
Chapter 6 FET Biasing
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(A) FIXED-BIAS CONFIGURATION
Vi&Vo:input & output ac levels
C1&C2: the coupling capacitors
Chapter 6 FET Biasing
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For dc analysis;
The zero-volt drop across RG permits replacing RG by a short-circuit equivalent, as
appearing in the network redrawn for the dc analysis.
(open for dc analysis &
low impedance (essentially
short circuit) for ac analysis.
The fact that the negative terminal of the battery is
connected directly to the defined positive potential of
VGS clearly reveals that the polarity of VGS is directly
opposite to that of VGG.
KVL in the clockwise direction will result in
Since VGG is a fixed dc supply, the voltage VGS is
fixed in magnitude, resulting in the notation “fixed-
bias configuration”.
The resulting level of drain current ID is now controlled
by Shockley’s equation.
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Since VGS is fixed quantity, its magnitude and sign can simply be substituted into Shockley’s
equation and the resulting level of ID calculated. Here, a mathematical solution to a FET
configuration is quite direct.
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On the other hand, graphical analysis would require a plot of Shockley’s equation.
Recall that choosing VGS=VP/2 will result in a drain current of IDSS/4 when plotting the
equation.
IDSS/2
O.3VP
The fixed level of V
has been
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In this analysis, four points defined by IDSS,
VP and intersection will be sufficient for plotting
the curve.
GS
superimposed as a vertical line at
VGS = -VGG.
The quiesc