Basic Precautions for an Analog Designer
Basic precautions and tips that an Analog Designer should know.
1. Minimum channel length of the transistor should be four to five times
the minimum feature size of the process. We do it, to make the λ of
the transistor low i.e. the rate of change of Id w.r.t to Vds is low.
2. Present art of analog design still uses the transistor in the saturation
region. So one should always keep Vgs of the Transistor 30% above the
3. One should always split the big transistor into small transistors having
width or length feature size ≤ 15µm.
4. W/L Ratio of transistors of the mirror circuit should be less than or
equal to 5, to ensure the proper matching of the transistors in the
layout. Otherwise, it results to the Systamatic Offset in the circuit.
5. One should make all the required pins in the schmetic before generating
the layout view. Because it’s difficult to add a pin in the layout view.
All IO pins should be a metal2 pins whereas Vdd and Ground should
be metal1 pins.
6. One should first simulate the circuit with the typical model parameters
of the devices. Since Vt of the trasistor can be anything between
Vt(Typical) ± 20%. So we check our circuit for the extreme cases i.e.
Vt + 20%, Vt − 20%. A transistor having Vt − 20% is called a fast
transistor and transistor having Vt+ 20% is called slow transistor. It’s
just a way to differentiate them. So with these fast and slow transistor
models we make four combination called nfpf, nfps, nspf, nsps, which
are known as process corners.
Now, once we are stisfied with the circuit performance with typical
models than we check it in different process corners, to take the process
variation into account. Vt is just one example of the process variation
there are others parameter too.
7. Its thumb rule that poly resistance has a 20% process variation whereas
well resistance has got 10%. But the poly resistance has got lower
temperature coefficent and lower Sheet Resistance than well resistance.
So we choose the resistance type