2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education
1
8051 AND ADVANCED PROCESSOR
ARCHITECTURES –
Lesson-4: Serial Data
Communication Input/Output
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education
2
Serial Interface SI
programmable for
λ half duplex synchronous serial or
λ full duplex asynchronous UART mode
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education
3
Two 8-bit SFRs
• SBUF (8 serial received bits or
transmission bits register depending
upon instruction is using SBUF as
source or destination)
• SCON (8-serial modes cum control
bits register) and SFR PCON.7 bit
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education
4
SBUF
λ Single SFR address for transmit and
received byte buffers when the serial output
or input is sent.
λ 0x99 the address of SI buffers.
λ SFR holds the SI transmission 8-bits when
it is written.
λ MOV 0x99, A instruction writes A into
transmission buffer from A register
λ MOV R1, 0x99 instruction read R1s register
from the receive buffer
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education
5
SCON
λ SFR to control the SI interface.
λ Three upper bits programs the modes as
0 or 1 or 2 or 3.
λ Mode 0 is half duplex synchronous.
λ Modes 1 or 2 or 3 are full duplex
asynchronous modes.
λ Bit SCON.4 enables or disables SI
receiver functions.
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education
6
SCON
λ Two bits SCON.3 and SCON.2 specify
the 8th bit to be transmitted and 8th bit
received when the mode is 2 or 3. A bit
SCON.1 enables or disables SI
transmitter interrupts (TI) on
completion of transmission.
λ Bit SCON.0 enables or disables SI
receiver interrupts (RI) on