INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2005 EDITION EXECUTIVE SUMMARY ACKNOWLEDGMENTS INTERNATIONAL ROADMAP COMMITTEE “Europe—Wolfgang Arden, Patrick Cogez, Mart Graef, Gerhard Goltz “Japan—Hidemi Ishiuchi, Toshihiko Osada “Korea— Joo-Tae Moon, Hyun-Chul Sohn “Taiwan—Mong-Song Liang, Chen-Hsi Lin, C.Y. Lu “U.S.A.—Pushkar Apte, Bob Doering, Paolo Gargini TECHNOLOGY WORKING GROUP KEY CONTRIBUTORS Chip-Size/Technology Node Study Group—Alan Allan, Chris Case, Chi-Shih Chang, Walter Class, Bob Doering, Donald Edenfeld, Denis Fandel, David Jensen, Andrew Kahng, Fred Lakani, Harry Levinson, Chris Long, Jeff Pettinato, Shizuo Sawada, Luan C. Tran, Peter Zeitzoff System Drivers and Design—Satoshi Akui, Ken Albin, Martin Anderson, Kanji Aoki, Larry Arledge, Yoshimi Asada, Kenji Asai, Woo-Hyun Baek, Bob Bentley, Kerry Bernstein, Valeria Bertacco, David Blaauw, Shawn Blanton, Ralf Brederlow, Mike Briere, Ben Brown, Ken Butler, Juan-Antonio Carballo, Mi-Chang Chang, C. Chen, Liang- Gee Chen, Young-Jung Choi, John Cohn, Don Cottrell, John Darringer, Hugo de Man, Stephane Donnay, Wolfgang Ecker, Dale Edwards, Yoshiharu Furui, Shinji Furuno, Jim Garrison, Sudhir Gowda, Carlo Guardiani, Hosam Haggag, Tamotsu Hiwatashi, Kelly A. Hopmeier, Mark Hsieh, Koichiro Ishibashi, Shih-Jie Jou, William Joyner, Andrew Kahng, Masaru Kakimoto, Haruhisa Kashiwagi, Stan Kaveckis, Jamil Kawa, Chang Kim, Chang-Hyun Kim, Jae-Suk Kim, Chi-Hau Kong, Victor Kravets, Dennis Lau, Seok-Joong Lee, C.C. Lee, Tsung-Hsien Lin, Gin-Kou Ma, Vinod Malhotra, Martin Margala, Grant Martin, Kazuya Masu, Masami Matsuzaki, Sury Maturi, Don McMillan, Anne Meixner, Y.N. Mo, Sharon Murray, Sani Nassif, Tomoji Nukiyama, Isao Okada, Nobuhiro Okano, Nobuto Ono, Sule Ozev, David Pan, Vijay Pitchumany, Carl Pixley, Daniel Purdy, John Rawlins, Bill Read, Kevin Redmond, John Rockway, Michael Rodgers, Wolfgang Rosenstiel, Toshitada Saito, Karem Sakallah, Joseph Sauerer, Jean- Pierre Schoellkopf, Peter Schwarz, Yahiro Shiotsuki, Gary Smith, Mani Soma, Leon Stok, Mikio Sumitani, Robert Taft, Tah-Kang Ting, Ryoichi Tomishige, Hiroki Tomoshige, Tadao Toyoda, Kunio Uchiyama, Maarten Vertregt, Piet Wambaq, Lawrence K Whitcomb, Jim Wieser, Bruce Wile, Alfred Wong, Ching-San Wu, Akihiro Yamada, Ichiro Yamamoto, David Yeh Test and Test Equipment—Joong-Bae Ahn, Katsuhiko Aiyoshi, Joel Amtsfield, Frank Anderson, Ken-ichi Anzou, Davide Appello, Dave Armstrong, Bassam Asfoor, Roger Barth, Vishwas Bhide, Mike Bienek, Dan Brija, Carl Buck, Scott Buckner, Yi Cai, Jwu E Chen, Paul Chen, Wei-ming Chi, Jeong-Ho Cho, Pat Cochran, Jack Courtney, Gordon Cowan, Guiseppe Paolo Crisenza, Dennis Eaton, Don Edenfeld, Mike Egloff, Kouichi Eguchi, Stefan Eichenberger, Michiaki Emori, Satoshi Fukumoto, Rudy Garcia, Anne Gattiker, Larry Gilg, Hosham Haggag, Mike Harris, Kazumi Hatayama, Ken Heiman, Klaus Dieter Hilliges, Masaki Hirano, Shigeyoshi Hirose, Hisao Horibe, Bernd Juling, Takayuki Katayama, Kyu-Cheul Kim, Takuya Kobayashi, Tomoaki Kobayashi, Jens Kober, John Lakoski, Matt Lauderdale, Chumg Len Lee, Kuen-Jong Lee, Kwan-Jong Lee, Mike Li, C. S. Lin, Charles Lin, Michio Maekawa, Peter Maxwell, Mike Mayberry, Dan Meyer, Shinji Mori, Peter Muhmenthaler, Luis Muller, Oliver Nagler, Yasushi Nakajima, Udaya Natarajan, Pierpaolo Nicosia, Phil Nigh, Yasumasa Nishimura, Kazuya Noguchi, Akira Ooishi, Bill Ortner, Hideharu Ozaki, David Pfaff, Bill Price, Rochit Rajsuman, James Rhodes, Paul Roddy, Mike Rodgers, Charles Rothschild, Masayuki Sato, Yasuo Sato, Ulrich Schoettmer, Fayez Sedarous, Rene Segers, Meng Lieh Sheu, Lee Song, Chauchin Su, Hiroyoshi Suzuki, Tetsuo Tada, I Shih Tseng, J. S Tseng, Masanori Ushikubo, Jody Van Horn, Don Van Overloop, Robert van Rijsinge, Erik Volkerink, Larry Wagner, Hitoshi Watanabe, Burnie West, Tom Williams, Cheng Wen Wu, Wen Ching Wu, Osamu Yamada, Mitsuo Yamazaki, Daniel Yang, Wen Kun Yang, Raymond Yin, Yervant Zorian Process Integration, Devices, and Structures—Yasushi Akasaka, Joe E. Brewer, C.P. Chao, Travis Chao, Osbert Cheng, S. C. Chien, James Chung, Simon Deleonibus, Theodore A. (Ted) Dellin, Carlos Diaz, Samuel K.H. Fung, J.C. Guo, Toshiro Hiramoto, Digh Hisamoto, Atsushi Hori, Ken Hsieh, W.Y. Hsieh, Margaret Huang, Jim Hutchby, Sung-Bo Hwang, Jiro Ida, Kiyotaka Imai, Young-Phil Kim, Tzu-Jae King, Dae-Hong Ko, Sang-Don Lee, Chia Wen Liang, Glen Lin, Y.T. Lin, Rich Liu, S.L. Lung, Mike Ma, Y.J. Mii, Naoki Nagashima, Takashi Nakamura, Tak H. Ning, Hidekazu Oda, Dong-Keun Park, Mark Rodder, Shizuo Sawada, Klaus Schruefer, Yee-Chaung See, Tae-Wook Seo, Kentaro Shibahara, Hun-Jong Shin, Riichiro Shirota, Thomas Skotnicki, Toshihiro Sugii, Yoshitaka Tadaki, Shuichi Tahara, Shinichi Takagi, Denny Tang, Luan C. Tran, Cheng taung Tsai, MJ Tsai, Ting S. Wang, Jason Woo, Chien Wu, Chung-Cheng Wu, Michael Wu, Qi Xiang, Geoffrey Yeap, Makoto Yoshimi, Peter Zeitzoff, Bin Zhao Radio Frequency and Analog/Mixed-signal Technologies for Wireless Communications—Hideo Aoyagi, Herbert S. Bennett, Ralf Brederlow, Doug Coolbaugh, Julio Costa, Peter E. Cottrell, Stefaan Decoutere, Jim Dunn, Mark Fedasiuk, Ronald Grundbacher, Dave Halchin, Yoshihiro Hayashi, Erwin Hijzen, Digh Hisamoto, W. Margaret Huang, Anthony A. Immorlica, Jay John, Alvin Joseph, Takahiro Kamei, Tom Kazior, Yukihiro Kiyota, Dim-Lee Kwong, Minh Le, Victor Liang, David McQuiddy, Jan-Erik Mueller, Marco Racanelli, Bernard Sautreuil, Hisashi (Sam) Shichijo, H.C. Tseng, Chuck Weitzel, Ching-San Wu, Peter Zampardi, Bin Zhao, Herbert Zirath, John Zolper Emerging Research Devices and Materials—Dimitri Antoniadis, Marc Baldo, Karl Berggren, Charles Black, Dawn Bonnell, George Bourianoff, Alex Bratkovski, Joe Brewer, John Carruthers, Sang Wook Cheong, Philippe Coronel, Supriyo Datta, Kristen De Meyer, Erik DeBenedictis, Simon Deleonibus, Alex Demkov, Steve Erwin, Michael Forshaw, Christian Gamrat, Michael Garner, Bruno Ghyselen, Jeff Grossman, Dan Hammerstrom, Daniel J.C. Herr, Toshiro Hiramoto, Susan Holl, James Hutchby, Berry Jonker, Ted Kamins, Richard Kiehl, Tsu-Jae King, Gerhard Klimeck, Zoran Krivokapic, Phil Kuekes, Louis Lome, Mark Lundstrom, Kathryn Moler, David Muller, Rama Muralidhar, Wei-Xin Ni, Tak Ning, Tobias Noll, Yuri Ponomarev, Muralidhar Ramachandran, Ramamoorthy Ramesh, Mark Reed, L. Rafael Reif, Lothar Risch, David A. Roberts, Vwani Roychowdhury, John Henry Scott, Sadasivan Shankar, Wei-Tsun Shiau, Kentaro Shibahara, Thomas Skotnicki, Morley Stone, Shinichi Takagi, Tom Theis, Jim Tour, Luan Tran, Rudolf M. Tromp, Ming-Jinn Tsai, Peter Varman, Eric Vogel, Kang Wang, Rainer Waser, Stan Williams, H.-S. Philip Wong, In Kyeong Yoo, Makoto Yoshimi, Peter Zeitzoff, Yuegang Zhang, Victor Zhirnov, Igor Zutic Front End Processes—Khaled Ahmed, Mauro Alessandri, Michael Alles, Olli Anttila, Luis Aparicio, Leo Archer, Souvik Banerjee, Joel Barnett, Tom Bastein, Twan Bearda, Larry Beckwith, Ivan (Skip) Berry, Roberto Bez, Frederic Boeuf, Bill Bowers, George Brown, Murray Bullis, Mayank T. Bulsara, Ahmed Busnaina, Jeff Butterbaugh, George K. Celler, Cetin Cetinkaya, Juanita Chambers, David Chang, Kow-Ming Chang, Mark Chang, Tien-Sheng Chao, S. C. Chen, Victor Chia, Albert Chin, Luigi Columbo, Michael Current, Tim Dalton, Carlos H. Diaz, Anthony (Tony) Dip, Bruce Doris, Roxanne Dulas, Laszlo Fabry, Jeff Farber, Sue Felch, Graham Fisher, Hideaki Fujiwara, Nobuo Fujiwara, Michael Fury, Glenn W. Gale, Ernst Gaulhofer, Hans Gossmann, Dinesh C. Gupta, Martin Gutsche, Greg Higashi, Dick Hockett, Andrew Hoff, Harry Hovel, Daniel Huang, J. M. Huang, Ru Huang, Tiao-Yuan Huang, Howard Huff, Bill Hughes, Makarem Hussein, Huang-Tsung Hwang, Yoshikazu Ibara, Simon Jang, Bob Johnston, Mototaka Kamoshida, Ho-Kyu Kang, Sien Kang, Seiichiro Kawamura, Bruce Kellerman, Yung Kim, Brian Kirkpatrick, Hiroshi Kitajima, Martin Knotter, Mitsuo Kohno, Daniel Koos, Alex Ku, Michitaka Kubota, Paul Langer, Larry Larson, Jeff Lauerhaas, Jeong-Gun Lee, Kun-Tack Lee, Lurng-Sheng Lee, Tan-Fu Lei, Meikei Leong, Didier Levy, Kuan Liao, Tom Lii, Hong Lin, Wen Lin, Jerry Liu, Shih-hsin Lo, Shrikant Lohokare, Don McCormack, Tom McKenna, Doug Meyer, Fred Meyer, Michihiko Mifuji, Ichiro Mizushima, Stephane Monfray, Jim Moreland, Nairn Moumen, Wolfgang Mueller, Anthony Muscat, Dave Myers, Toufic Najia, Toshiro Nakanishi, Sadao Nakashima, Yasuo Nara, Masaaki Niwa, Faran Nouri, Helmut Oefner, Atsushi Ogura, Toshihide Ohgata, Carl Osburn, Jin-Goo Park, Shiesen Peng, Darryl Peters, Gerd Pfeiffer, Francesco Pipia, Noel Poduje, Jagdish Prasad, Krishnaswamy Ramkumar, K. V. Ravi, Rick Reidy, Karen Reinhardt, Jae-Sung Roh, Ed Rutter, Pete Sandow, Tom Seidel, Hwa-il Seo, Giorgio Servalli, Jim Shen, Hyun-Soo Shin, Stephen Silverman, Greg Smith, Jong-Won Sohn, Chris Sparks, Bob Standley, Jack Thomas, Carl Treadwell, Hong-Hsiang Tsai, Bing-Yue Tsui, Hidetsugu Uchida, Jason Underwood, Steven Verhaverbeke, Peter Wagner, Mike Walden, Masaharu Watanabe, Neil Weaver, Susanne Weizbauer, Jeff Wetzel, Ted White, Rick Wise, S. G. Wuu Lithography—Jin-Ho Ahn, Hiroshi Arimoto, Emanuele Baracchi, R. K. Chen, T. Y. Chen, John Cheng, HanKu Cho, Han-Ku Cho, Jae-Sung Choi, Jin-Young Choi, Ron Chu, Kevin Cummings, Giang Dao, Akihiro Endo, Ted Fedynyshyn, Gene Fuller, Reiner Garreis, Jan Willem Gemmink, Janice Golda, George Gomba, Maureen Hanratty, Isamu Hanyu, Naoya Hayashi, Scott Hector, Dan Herr, Iwao Higashikawa, B. Y. Hsu, Jerry Huang, J.R. Hwang, Koki Inoue, Rainer Kaesmaier, Masaomi Kameyama, S. H. Kau, Yoshio Kawai, Beth Kells, Hyeong-Soo Kim, Kurt Kimmel, Y. C. Ku, H. C. Kuo, Keishiro Kurihara, Benjamin Lin, Burn J. Lin, C. H. Lin, J. T. Lin, John Lin, Susumu Mori, Shigeru Moriya, Shinji Okazaki, Yoshimitsu Okuda, Se-Jin Park, Dave Patterson, S. Y. Po, Sergei Postnikov, Chris Progler, Morde Rothschild, Masaru Sasago, Gil Shelden, Phil Seidel, C. L. Shih, Kazuyuki Suko, Takashi Taguchi, Yoichi Takehana, Hidehito Tanaka, Rebecca Tang, Tsuneo Terasawa, Walt Trybula, H. C. Tsai, Takayuki Uchiyama, Gerd Unger, Mauro Vasconi, Keiji Wada, Ulrich Wagemann, C. M. Wang, Lon A. Wang, M. H. Wang, Phil Ware, John Wiesner, Grant Willson, Masaki Yamabe, Yuichi Yamada, Atsuko Yamaguchi, Tadayuki Yamaguchi, Thomas Zell Interconnect—Nobuo Aoi, Lucile Arnaud, Hans-Joachim Barth, Ivan Berry, Christopher Case, Kow-Ming Chang, Bau-Tong Dai, Mamoru Endo, Manfred Engelhardt, Alexis Farcy, Paul Feeney, Akira Fukunaga, Bob Geffken, Marilyn Glendenning, Narishi Gonohe, Dirk Gravesteijn, Harold Hosack, Calvin Hsueh, Calvin Hsueh, Fred Huang, Masayoshi Imai, Makiko Kageyama, Si-Bum Kim, Mauro Kobrinsky, Noh-Jung Kwak, Han-Choon Lee, Hyeon-Deok Lee, Hyeon-Dyuck Lee, Gene Li, J.D. Luttmer, Mike Mills, Hiroshi Miyazaki, Ken Monnig, N.S. Nagaraj, Tomoji Nakamura, Gary Ray, Rick Reidy, Guenther Schindler, Hideki Shibata, Winston Shue, Hyunchul Sohn, Michele Stucchi, Tony Tsai, Manabu Tsujimura, Kazuyoshi Ueno, David Wu, Osamu Yamazaki, C. H. Yu, Douglas Yu Factory Integration—Hiroyuki Akimori, Josef Bichlmeier, Mike Bufono, Hugo S.C. Chang, Jonathan Chang, Wesley W. H. Chang, Al Chasey, Allan Chen, Thomas Chen, Gilbert Chiang, Eric Christensen, Ron Denison, Klaus Eberhardt, Patrick Fernandez, Neil Fisher, Len Foster, Ashwin Ghatalia, Barbara Goldstein, Arieh Greenberg, Sven Hahn, Chung Soo Han, Parris Hawkins, Michio Honma, George Horn, J. J. Hsu, Giichi Inoue, Junji Iwasaki, Mani Janakiram, Melvin Jung, Kazuhiro Kakizaki, Franklin Kalk, Atsuhiko Kato, Shigeru Kobayashi, Shoichi Kodama, Todd Lasater, In-Kyu Lee, Ya-Shian Li, Ricky Lin, Maggie Liu, Span Lu, Les Marshall, Dave Miller, Akira Mitsui, Eckhard Müller, Hideki Nakajima, Seiichi Nakazawa, Richard Oechsner, Mikio Otani, Chel-Soo Park, S. H. Park, Suk-Hee Park, Jeff Pettinato, Dev Pillai, Lisa Pivin, Scott Pugh, Adrian Pyke, JB Ragothaman, Claus Schneider, Mike Schwartz, Steve Seall, Marlin Shopbell, Arnie Steinman, Dan Stevens, Peggy Su, Abol Taghizadeh, Junichi Takeuchi, T.M. Tseng, K.R. Vadivazhagu, Joost van Herk, Philippe Vialletelle, Harvey Wohlwend, Hiromi Yajima, Makoto Yamamoto, William W.L. Yuan Assembly and Packaging—Joe Adam, Steve Adamson, Mark Bird, Bill Bottoms, Kwang-Yu Byun, Chi-Shih Chang, Bill Chen, Carl Chen, Paul Chen, Wen Yan Chen, David Cheng, P. K. Chiang, Young-Bok Choi, Tsung-Yao Chu, Dan Evans, Nobuo Futawatari, George Harman, Shuya Haruguchi, Ryo Haruta, James Ho, Ted Ho, S. P. Hsu, Chender Huang, Lewis L. Hwan, Mahandevan Iyer, Hisao Kasuga, Michitaka Kimura, Eric Kung, Dong-Ho Lee, R.S. Lee, Simon Li, Mirng-Ji Lii, M.S. Lin, Hermen Liu, Shelton Lu, Hirofumi Nakajima, Kieth Newman, Kazuo Nishiyama, Bob Pfahl, Klaus Pressel, Bernd Roemer, Young-Bin Sun, Coen Tak, Kuniaki Takahashi, Takashi Takata, Ho-Ming Tong, F.J. Tsai, Ruenn-Bo Tsai, Shigeyuki Ueda, Shoji Uegaki, Henry Utsunomiya, Juergan Wolf, David Wu, Enboa Wu, Vincent Yang, Wen Kun Yang, Wilson Yang, Zhiping Yang, Eiji Yoshida Environment, Safety, and Health—Junichi Aoyama, Hans-Peter Bipp, Roger Chang, George Chen, Steve Cho, Geun-Min Choi, Terry Francis, Nigel Hsu, Ho-Song Hwang, Francesca Illuzzi, Jim Jewett, CY Kao, Shou-Nan Li, C.N. Lin, Sam Lin, Mary Majors, Ed McCarthy, Mike Mocella, Joseph K.C. Mou, Larry Novak, Takayuki Oogoshi, Chyr-Hwan Suen, Tetsu Tomine, Ming Shih Tsai, Sy-Wen Wong, Ted Wong, Walter Worth, Tim Yeakley, Jung-Pin Yu Yield Enhancement—Scott Anderson, Hyun-Chul Baek, Tracey Boswell, Mark Camenzind, Jan Cavelaars, Kristen Cavicchi, C. H. Chang, Chung-I Chang, Jeff Chapman, Chan-Yuan Chen, Victor Chia, Do-Hyun Cho, Uri Cho, James S. Clarke, J-M. Collard, Mark Crockett, Dirk de Vries, John Degenova, James Dougan, Diane Dougherty, Francois Finck, Tom Gutowski, Jeffrey Hanson, Rob Henderson, Benoit Hirschberger, Christoph Hocke, Ji Ho-Hong, J.J. Hsu, Jim Huang, Steven Hues, Yoji Ichiyasu, Masahiko Ikeno, Francesca Illuzzi, Rick Jarvis, Jim Jewett, Wang Jiun-Fang, Billy Jones, C. S. Jou, Keith Kerwin, John Kurowski, Sumio Kuwabara, M T Liu, Mingo Liu, Y.T. Liu, Chris Long, Michael Lurie, Steven Ma, James McAndrew, Robert McDonald, Mike McIntyre, Len Mei, Yoko Miyazaki, Fumio Mizuno, Mansour Moinpour, William Moore, Chris Muller, Yoshinori Nagatsuka, Andreas Neuber, Kazuo Nishihagi, Andreas Nutsch, Joseph O’Sullivan, Akira Okamoto, Takanori Ozawa, Shang-Kyun Park, Kevin T. Pate, Dilip Patel, Lothar Pfitzner, Dieter Rathei, Ron Remke, Mike Retersdorf, Ralph Richardson, J. Ritchison, Dave Roberts, Dan Rodier, John Rydzewski, Koichi Sakurai, Tony Schleisman, Sarah Schoen, Hisaharu Seita, C. H. Shen, Yoshimi Shiramizu, Val Stradzs, Ed Terrell, Ines Thurner, Bart Tillotson, Ken Tobin, Stephen Toebes, Jimmy Tseng, Ken Tsugane, Hank Walker, Tings Wang, Jian Wei, Dan Wilcox, Hubert Winzig, Walter Worth, Albert Wu, Yuichiro Yamazaki , C. S. Yang Metrology—John Allgair, Chas Archie, Mike Bishop, Dick Brundle, Michele Buckley, Ben Bunday, Hugo Celio, Fang-Cheng Chen, Man-Ho Cho, Alain Diebold, Shinji Fujii, Dick Hockett, Jia-Rui Hu, Chin Yi Huang, P.Y. Hung, Masahiko Ikeno, Jung-Yeul Jang, Soo-Bok Jin, David Joy, Eiichi Kawamura, Chul-Hong Kim, Steve Knight, Isao Kojima, King Lee, Pete Lipscomb, Ulrich Mantz, Jack Martinez, Joaquin Martinez, Fumio Mizuno, Kevin Monahan, Kazuo Nishihagi, Baw-Ching Perng, Noel Poduje, Michael Postek, Jimmy Price, Gary Rubloff, Jyu-Horng Shieh, Jyu-Horng Shieh, Chin Soobok, Rien Stoup, Aritoshi Sugimoto, Vladimir Ukraintsev, Brad van Eck, Mauro Vasconi, Dick T.A.P. Verkleij, Andras Vladar, Dan Wack, Atsuko Yamaguchi, Yuichiro Yamazaki, Stefan Zollner Modeling and Simulation—Doelf Aemmer, Susumu Asada, Vivek Bakshi, Augusto Benvenuti, Lars Bomholt, Ingo Bork, Stephen M. Cea, Y. T. Chia, Yong-Soo Cho, Jae-Hoon Choi, An De Keersgieter, Wolfgang Demmerle, Andreas Erdmann, Masato Fujinaga, Youichi Hayashi, Anco Heringa, Howard Huff, Noriyuki Ishihara, Herve Jaouen, Christian Kalus, Mitsunori Kimura, Karson Knutson, Jun Komachi, Erasmus Langer, Giles Le Carval, Keun-Ho Lee, Keun-Ho Lee, Jürgen Lorenz, Chris A. Mack, Meyya Meyyappan, Rainer Minixhofer, Wolfgang Molzer, Christoph Müller, Mitsutoshi Nakamura, Seiji Ogata, Marius Orlowski, Shane Palmer, Paul Pfäffli, Peter Pichler, Concetta Riccobene, Shigeo Satoh, F. Schellenberg, Vivek Singh, Walt Trybula, Peter L.G. Ventzek, Tetsunori Wada, Tiger Wang, J. Wiley, Reinout Woltjer, Robert Wright, Jeff Wu, Bernhard Wunderle, Peter Zeitzoff, Song Zhao REGIONAL SUPPORT TEAMS We acknowledge and thank the regional teams for their support: “Europe—Infineon—Carola Siebert, SEMI Europe—Johanna Turpeinen, Fred Kolbe, and Walter Roessger “Japan—Yasuaki Hokari “Korea—Jae-Min Jun “Taiwan—Celia Shih “USA—Yumiko Takamori, Linda Wilson Intel meeting support team—Sally Yanez, Barbara Pebworth International SEMATECH—Dave Anderson, Debra Elley, Sue Gnat, Mario Gonzales, Sarah Mangum, Marilyn Redmond, Bob Ruliffson, Donna Towery National Science Foundation—Mihail Roco SEMI North America— Pat Gardner, Jody Sullivan SIA—Judy Ajifu Rodgers i THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 FOREWORD The International Technology Roadmap for Semiconductors (ITRS) is the result of a worldwide consensus-building process. This document predicts the main trends in the semiconductor industry spanning across 15 years into the future. The participation of experts from Europe, Japan, Korea, and Taiwan as well as the U.S.A. ensures that the ITRS is a valid source of guidance for the semiconductor industry as we strive to extend the historical advancement of semiconductor technology and the worldwide integrated circuit (IC) market. These five regions jointly sponsor the ITRS. The Semiconductor Industry Association (SIA) coordinated the first efforts of producing what was originally The National Technology Roadmap for Semiconductors (NTRS). The semiconductor industry became a global industry in the 1990s, as many semiconductor chip manufacturers established manufacturing or assembly facilities in multiple regions of the world. This realization led to the creation of the International Technology Roadmap for Semiconductors in the late 90s. The invitation to cooperate on the ITRS was extended by the SIA at the World Semiconductor Council in April 1998 to Europe, Japan, Korea, and Taiwan. Since then, full revisions of the ITRS were produced in 1999, 2001 and 2003; ITRS updates were produced in the even-numbered years (2000, 2002, 2004). The 2005 ITRS represents a major departure from the previous versions of Roadmaps because it removes the concept of “technology node” as the main pace setter for the IC industry. In the past, DRAM products set the technology pace by quadrupling the number of bits every three years with the introduction of a new major technology generation. The relation among transistor density (4×) and metal half-pitch (×0.7) and year of introduction (three-year) remained constant from the mid-70s to the mid-90s. The reduction from generation to generation of the DRAM half-pitch of metal by 30% (0.7× the previous technology generation) identified a “technology node.” However, the increase in the number of bits by four times from one technology node to the next led to a continuous increase in die size that eventually negatively affected the economics of this silicon cycle. In an attempt to minimize the increase in die size many IC companies accelerated the speed at which new technology nodes were introduced from a three-year cycle to a 2–2 ½-year cycle in the second half of the 90s. As device features become smaller, MPU and Flash technologies have been approaching (and in some cases producing) features even smaller than DRAM. Additionally, MPU and Flash products have been introduced at a comparable or, at times, even faster pace than DRAMs. As a result, the use of a single number (such as a technology node) derived from the half-pitch of DRAM no longer suffices to characterize the whole semiconductor industry. The 2005 ITRS addresses an independent measure of the technology pace of DRAM, of MPU, and of Flash products. Another change in the 2005 ITRS indicates the growing interest in new nanoscale devices representing alternatives to CMOS. Emerging Research Devices topics are now addressed in a separate chapter from the Process Integration, Devices, and Structures chapter. Indeed, even though CMOS is (and will remain) the industry workhorse up to and beyond the year 2020, it is anticipated that new devices will be introduced in the latter half of the next decade utilizing different and new ways of processing and storing information. Most of the proposed devices rely very heavily on new material properties and therefore, a new sub-chapter on Emerging Research Materials has been added to the ERD chapter. In conclusion, it is the purpose of the ITRS documents to provide a reference of requirements, potential solutions, and their timing for the semiconductor industry. This objective has been accomplished by providing a forum for international discussion, cooperation, and agreement among the leading semiconductor manufacturers and the leading suppliers of equipment, materials, and software, as well as researchers from university, consortia, and government labs. The ITRS documents have become and remain a truly common reference for the entire semiconductor industry. Indeed, the cooperative efforts of the ITRS participants have fostered cooperation among international consortia, universities, and research institutions around the world. It is hoped that the 2005 ITRS will further contribute to stimulate cooperative R&D investments so that the financial burden can be more uniformly shared by the whole industry. It is also hoped that the 2005 ITRS will continue to stimulate the fundamental elements that encourage innovation in individual companies. ii THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 iii THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 TABLE OF CONTENTS Foreword ................................................................................................................................ i Introduction ...........................................................................................................................1 Overview..........................................................................................................................................1 Overall Roadmap Process and Structure ........................................................................................2 Roadmapping Process.................................................................................................................................2 Roadmap Content ........................................................................................................................................3 Technology Characteristics..........................................................................................................................4 Technology Pacing.......................................................................................................................................5 Roadmap Scope...........................................................................................................................................8 Position on Potential Solutions.....................................................................................................................9 2005 ITRS Special Topics............................................................................................................................9 Grand Challenges ...............................................................................................................11 Overview........................................................................................................................................11 In the Near Term (through ~2013).................................................................................................11 Enhancing Performance.............................................................................................................................11 Cost-Effective Manufacturing .....................................................................................................................14 In The Long Term (~2014 through 2020) ......................................................................................16 Enhancing Performance.............................................................................................................................16 Cost-Effective Manufacturing .....................................................................................................................17 What is New for 2005—the Working Group Summaries .....................................................19 System Drivers ..............................................................................................................................19 Design ...........................................................................................................................................21 Difficult Challenges.....................................................................................................................................22 Test and Test Equipment...............................................................................................................23 Difficult Challenges.....................................................................................................................................23 Process Integration, Devices and Structures.................................................................................25 Difficult Challenges.....................................................................................................................................26 Radio Frequency and Analog/Mixed-Signal Technologies for Wireless Communications ............28 Difficult Challenges.....................................................................................................................................29 Emerging Research Devices .........................................................................................................31 Difficult Challenges.....................................................................................................................................32 Front End Processes .....................................................................................................................33 Difficult Challenges.....................................................................................................................................36 Lithography....................................................................................................................................38 Difficult Challenges.....................................................................................................................................39 Interconnect ...................................................................................................................................41 Difficult Challenges.....................................................................................................................................42 Factory Integration.........................................................................................................................43 Difficult Challenges.....................................................................................................................................44 Assembly and Packaging ..............................................................................................................47 Difficult Challenges.....................................................................................................................................47 Environment, Safety, and Health ...................................................................................................49 Difficult Challenges.....................................................................................................................................50 Yield Enhancement........................................................................................................................52 Difficult Challenges.....................................................................................................................................53 iv THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 Metrology .......................................................................................................................................54 Difficult Challenges ....................................................................................................................................55 Modeling and Simulation ...............................................................................................................56 Difficult Challenges ....................................................................................................................................57 Overall Roadmap Technology Characteristics.................................................................... 59 Background....................................................................................................................................59 Overview of 2005 Revisions ..........................................................................................................59 Definitions...................................................................................................................................................59 Roadmap Timeline .....................................................................................................................................61 Product Generations and Chip-Size Model................................................................................................64 Chip-Size, Lithographic-Field, and Wafer-Size Trends..............................................................................73 Performance of Packaged Chips ...............................................................................................................75 Electrical Defect Density ............................................................................................................................80 Power Supply and Power Dissipation ........................................................................................................81 Cost ............................................................................................................................................................83 Glossary ............................................................................................................................. 86 LIST OF FIGURES Figure 1 Composition of the ITRS Teams—1288 Global Participants...........................3 Figure 2 2005 Definition of Pitches ................................................................................6 Figure 3 A Typical Production “Ramp” Curve ................................................................6 Figure 4 Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution ..................................................8 Figure 5 Moore’s Law and More ....................................................................................9 Figure 6 MOS Transistor Scaling—1974 to present ....................................................61 Figure 7 Scaling Calculator..........................................................................................61 Figure 8 2005 ITRS—Half Pitch and Gate Length Trends...........................................63 Figure 9 2005 ITRS Product Function Size Trends: MPU Logic Gate Size (4-transistor); Memory Cell Size [SRAM (6-transistor); Flash (SLC and MLC), and DRAM (transistor + capacitor)] ......................................................................68 Figure 10 2005 ITRS Product Technology Trends: Product Functions/Chip and Industry Average “Moore’s Law” Trends........................................................68 v THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 LIST OF TABLES Table A Improvement Trends for ICs Enabled by Feature Scaling...............................1 Table B ITRS Table Structure—Key Lithography-related Characteristics by Product ..5 Table ITWG 1 Major Product Market Segments and Impact on System Drivers ..................20 Table ITWG 2 Overall Design Technology Challenges.........................................................22 Table ITWG 3 Summary of Key Test Drivers, Challenges and Opportunities ......................24 Table ITWG 4 Process Integration Difficult Challenges ........................................................26 Table ITWG 5 RF and Analog Mixed-Signal (RF and AMS) Technologies for Wireless Communications Difficult Challenges .............................................29 Table ITWG 6 Emerging Research Device Technologies Difficult Challenges.....................32 Table ITWG 7 Front End Processes Difficult Challenges .....................................................36 Table ITWG 8 Lithography Difficult Challenges ....................................................................39 Table ITWG 9 Interconnect Difficult Challenges ...................................................................42 Table ITWG 10 Factory Integration Difficult Challenges .........................................................45 Table ITWG 11 Assembly and Packaging Difficult Challenges...............................................47 Table ITWG 12 ESH Difficult Challenges................................................................................50 Table ITWG 12 ESH Difficult Challenges (continued).............................................................51 Table ITWG 13 Yield Enhancement Difficult Challenges........................................................53 Table ITWG 14 Metrology Difficult Challenges .......................................................................55 Table ITWG 15 Modeling and Simulation Difficult Challenges................................................57 Table C Rounded versus Actual Trend Numbers (DRAM Product Trend Example)...62 Table 1a Product Generations and Chip Size Model Technology Trend Targets— Near-term Years ............................................................................................65 Table 1b Product Generations and Chip Size Model Technology Trend Targets— Long-term Years............................................................................................65 Table 1c DRAM and Flash Production Product Generations and Chip Size Model— Near-term Years ............................................................................................66 Table 1d DRAM and Flash Production Product Generations and Chip Size Model— Long-term Years............................................................................................67 Table 1e DRAM Introduction Product Generations and Chip Size Model— Near-term Years ............................................................................................69 Table 1f DRAM Introduction Product Generations and Chip Size Model— Long-term Years............................................................................................69 Table 1g MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model—Near-term Years .......................................................70 Table 1h MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model—Long-term Years .......................................................71 Table 1i High-Performance MPU and ASIC Product Generations and Chip Size Model—Near-term Years ..............................................................72 Table 1j High-Performance MPU and ASIC Product Generations and Chip Size Model—Long-term Years ..............................................................72 Table 2a Lithographic-Field and Wafer-Size Trends—Near-term Years ......................75 Table 2b Lithographic-Field and Wafer Size Trends—Long-term Years ......................75 vi THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 Table 3a Performance of Packaged Chips: Number of Pads and Pins— Near-term Years ............................................................................................76 Table 3b Performance of Packaged Chips: Number of Pads and Pins— Long-term Years ............................................................................................76 Table 4a Performance and Package Chips: Pads, Cost—Near-term Years ................78 Table 4b Performance and Package Chips: Pads, Cost—Long-term Years ................78 Table 4c Performance and Package Chips: Frequency On-chip Wiring Levels— Near-term Years ............................................................................................79 Table 4d Performance and Package Chips: Frequency On-chip Wiring Levels— Long-term Years ............................................................................................79 Table 5a Electrical Defects—Near-term Years.............................................................80 Table 5b Electrical Defects—Long-term Years.............................................................80 Table 6a Power Supply and Power Dissipation—Near-term Years..............................81 Table 6b Power Supply and Power Dissipation—Long-term Years .............................82 Table 7a Cost—Near-term Years .................................................................................84 Table 7b Cost—Long-term Years .................................................................................84 Introduction 1 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 INTRODUCTION OVERVIEW For four decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in its products. The principal categories of improvement trends are shown in Table A with examples of each. Most of these trends have resulted principally from the industry’s ability to exponentially decrease the minimum feature sizes used to fabricate integrated circuits. Of course, the most frequently cited trend is in integration level, which is usually expressed as Moore’s Law (that is, the number of components per chip doubles every 24 months). The most significant trend is the decreasing cost-per-function, which has led to significant improvements of productivity and quality of life through proliferation of computers, electronic communication, and consumer electronics. Table A Improvement Trends for ICs Enabled by Feature Scaling TREND EXAMPLE Integration Level Components/chip, Moore’s Law Cost Cost per function Speed Microprocessor clock rate, GHz Power Laptop or cell phone battery life Compactness Small and light-weight products Functionality Nonvolatile memory, imager All of these improvement trends, sometimes called “scaling” trends, have been enabled by large R&D investments. In the last two decades, the growing size of the required investments has motivated industry collaboration and spawned many R&D partnerships, consortia, and other cooperative ventures. The International Technology Roadmap for Semiconductors (ITRS) has been an especially successful worldwide cooperation. It presents an industry-wide consensus on the “best current estimate” of the industry’s research and development needs out to a 15-year horizon. As such, it provides a guide to the efforts of companies, research organizations, and governments. The ITRS has improved the quality of R&D investment decisions made at all levels and has helped channel research efforts to areas that truly need research breakthroughs. Since its inception in 1992, a basic premise of the Roadmap has been that continued scaling of microelectronics would further reduce the cost per function (historically, ~25–29%% per year) and promote market growth for integrated circuits (historically averaging ~17% per year, but maturing to slower growth in more recent history). Thus, the Roadmap has been put together in the spirit of a challenge—essentially, “What technical capabilities need to be developed for the industry to stay on Moore’s Law and the other trends?” This challenge has become so formidable that increasingly more of the semiconductor industry’s research effort, including consortia and collaboration with suppliers, has been shared in a precompetitive environment. The 2005 ITRS is the fourth fully revised edition and the result of the continued worldwide consensus building process. The participation of semiconductor experts from Europe, Japan, Korea, Taiwan, and the U.S.A. ensures that the 2005 ITRS continues to be the definitive source of guidance for semiconductor research as we strive to extend the historical advancement of semiconductor technology and the integrated circuit market. The diverse expertise and dedicated efforts that this international effort mobilized have brought the Roadmap to a new level of worldwide consensus about future semiconductor technology requirements. The complete 2005 ITRS and past editions of the ITRS are available for viewing and printing as electronic documents at the Internet web site http://public.itrs.net. 2 Introduction THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 OVERALL ROADMAP PROCESS AND STRUCTURE ROADMAPPING PROCESS Overall coordination of the ITRS process is the responsibility of the International Roadmap Committee (IRC), which has two-to-four members from each sponsoring region (Europe, Japan, Korea, Taiwan, and the U.S.A.). The principal IRC functions include the following: • Providing guidance/coordination for the international technology working groups (ITWGs) • Hosting the ITRS Workshops • Editing the ITRS The international technology working groups write the corresponding technology-area chapters of the ITRS. The ITWGs are of two types: Focus ITWGs and Crosscut ITWGs. The Focus ITWGs correspond to typical sub-activities that sequentially span the Design/Process/Test/Package product flow for integrated circuits. The Crosscut ITWGs represent important supporting activities that tend to individually overlap with the “product flow” at multiple critical points. For the 2005 ITRS, the Focus ITWGs are the following: • System Drivers • Design • Test and Test Equipment • Process Integration, Devices, and Structures • RF and Analog / Mixed-signal Technologies for Wireless Communications • Emerging Research Devices / Emerging Research Materials • Front End Processes • Lithography • Interconnect • Factory Integration • Assembly and Packaging Crosscut ITWGs are the following: • Environment, Safety, and Health • Yield Enhancement • Metrology • Modeling and Simulation The ITWGs are composed of experts from industry (chip-makers as well as their equipment and materials suppliers), government research organizations, and universities. In 2005, 1288 experts participated in revising the Roadmap (a 27% increase from the 2003 participants). The composition of the total TWG membership is analyzed in Figure 1. The demographics per ITWG reflect the affiliations that populate the technology domains. For example, with a longer- term focus area such as Emerging Research Devices, the percentage of research participants is higher than suppliers. In the process technologies of Front End Processes, Lithography, and Interconnect, the percentages of suppliers reflect the equipment/materials suppliers’ participation as much higher due to the near-term requirements that must be addressed. Introduction 3 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 Figure 1 Composition of the ITRS Teams—1288 Global Participants For the 2005 edition, three ITRS meetings were held worldwide as follows: Munich, Germany (sponsored by the ESIA and hosted by Infineon); San Francisco, U.S.A., sponsored by the SIA and organized by SEMATECH; and Seoul, Korea (sponsored and hosted by the KSIA). These meetings provided the main forums for face-to-face discussions among the members of each ITWG and coordination among the different ITWGs. In addition, the ITRS teams hold public ITRS conferences bi-annually to present the latest Roadmap information and to solicit feedback from the semiconductor industry at-large. The ITRS is released annually, with updates and corrections to data tables each even-numbered year (such as 2000, 2002, 2004) while complete editions are released each odd-numbered year (2001, 2003, 2005). This ITRS process thus ensures continual assessment of the semiconductor industry’s near and long-term needs. It also allows the teams to correlate in a timely fashion the ITRS projections to most recent research and development breakthroughs that may provide solutions to those needs. ROADMAP CONTENT The ITRS identifies the principal technology needs to guide the shared research, showing the “targets” that need to be met. These targets are as much as possible quantified and expressed in tables, showing the evolution of key parameters over time. Accompanying text explains and clarifies the numbers contained in the tables where appropriate. The ITRS further distinguishes between different maturity or confidence levels, represented by colors in the tables, for these targets: Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known ¡ Manufacturable solutions are NOT known The first situation, “Manufacturable solutions exist, and are being optimized,” indicates that the target is achievable with the currently available technology and tools, at production-worthy cost and performance. The yellow color is used when additional development is needed to achieve that target. However, the solution is already identified and experts are confident that it will demonstrate the required capabilities in time for production start. The situation “Interim Solutions are Known” means that limitations of available solutions will not delay the start of production, but work-arounds will be initially employed in these cases. Subsequent improvement is expected to close any gaps for production performance in areas such as process control, yield, and productivity. The fourth and last situation is highlighted as “red” on the Roadmap Euro pe (124) 10 % Japan (223) 17 % Ko re a (60) 5% Taiwan (172) 13 % US A (709) 55% 2005 ITRS Members by Region Co ns o rt ia / Re s e a rc h Ins t itute / Univ e rs ity (274) 21% Equipm e nt / Mate rials S upplie rs (263) 20 % Chip make rs (677) 53% Othe rs (7 4 ) 6% 2005 ITRS Members by Affiliation 4 Introduction THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 technology requirements tables and has been referred to as the “Red Brick Wall” since the beginning of ITRS. (The “red” is officially on the Roadmap to clearly warn where progress might end if tangible breakthroughs are not achieved in the future.) Numbers in the red regime, therefore, are only meant as warnings and should not be interpreted as “targets” on the Roadmap. For some Roadmap readers, the “red” designation may not have adequately served its sole purpose of highlighting significant and exciting challenges. There can be a tendency to view any number in the Roadmap as “on the road to sure implementation” regardless of its color. To do so would be a serious mistake. “Red” indicates where there are no “known manufacturable solutions” (of reasonable confidence) to continued scaling in some aspect of the semiconductor technology. An analysis of “red” usage might classify the “red” parameters into two categories: 1. where the consensus is that the particular value will ultimately be achieved (perhaps late), but for which the industry doesn’t have much confidence in any currently proposed solution(s), or 2. where the consensus is that the value will never be achieved (for example, some “work-around” will render it irrelevant or progress will indeed end) To achieve the red parameters of the first category, breakthroughs in research are needed. It is hoped that such breakthroughs would result in the “red” turning to “yellow” (manufacturable solutions are known) and, ultimately “white” (manufacturable solutions are known and are being optimized) in future editions of ITRS. As indicated in the overview, the Roadmap has been put together in the spirit of defining what technical capabilities the industry needs to develop in order to stay on Moore’s Law and the other trends, and when. So the ITRS is not so much a forecasting exercise as a way to indicate where research should focus to continue Moore’s law. In that initial “challenge” spirit, the Overall Roadmap Technology Characteristics (ORTC) team updates key high-level technology needs, which establish some common reference points to maintain consistency among the chapters. The high-level targets expressed in the ORTC tables are based in part on the compelling economic strategy of maintaining the historical high rate of advancement in integrated circuit technologies. A good example of that is the adoption, in this 2005 edition of the Roadmap, of 2012 as the year of introduction of 450 mm wafers in volume production. While this date was based on an economics model, it should not be seen so much as a forecast at this stage, than as a way to induce the working groups to focus on the various technical issues associated with such a transition to 450 mm. Over the years, however, the Roadmap has sometimes been seen as a self-fulfilling prophecy. To a certain extent this is also a valid view, as companies have benchmarked each other against the roadmap, and it proved itself very effective in providing thrust for research. So it is not unreasonable to use the Roadmap targets, when manufacturing solutions or acceptable workarounds are known, as guidelines to forecasting exercises. What these targets should never be used for, however, is as basis for legal claims in commercial disputes or other circumstances. In particular, the participation in the ITRS roadmapping process does not imply in any way a commitment by any of the participating companies to comply with the Roadmap targets. We recall that the ITRS is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual product or equipment. TECHNOLOGY CHARACTERISTICS As mentioned above, a central part of the IRC guidance and coordination is provided through the initial creation (as well as continued updating) of a set of Overall Roadmap Technology Characteristics (ORTC) tables. Each ITWG chapter contains several principal tables. They are individual ITWGs’ technology requirements tables patterned after the ORTC tables. For the 2005 ITRS, the ORTC and technology requirements tables are fully annualized and in both the “Near-term Years” (2005, 2006… through 2013) and “Long-term Years” (2014, 2015 … through 2020) This format is illustrated in Table B, which contains a few key rows from lithography-related ORTC Table 1a and 1b, including the new Flash product uncontacted polysilicon half-pitch technology trend line item. Only the DRAM stagger-contacted M1 half pitch line item is used as a standard header for all the 2005 ITRS ITWG tables. At the discretion of the ITWGs, other product technology trend driver line items may be selected from ORTC Table 1a and 1b for use in their ITWG tables as overall headers indicating key drivers for their tables. Introduction 5 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 Table B ITRS Table Structure—Key Lithography-related Characteristics by Product Near-term Years YEAR OF PRODUCTION 2005 2006 2007 2008 2009 2010 2011 2012 2013 DRAM stagger-contacted Metal 1 (M1) ½ Pitch (nm) 80 70 65 57 50 45 40 36 32 MPU/ASIC stagger-contacted Metal 1 (M1)½ Pitch (nm) 90 78 68 59 52 45 40 36 32 Flash Uncontacted Poly Si ½ Pitch (nm) 76 64 57 51 45 40 36 32 28 MPU Printed Gate Length (nm) 54 48 42 38 34 30 27 24 21 MPU Physical Gate Length (nm) 32 28 25 23 20 18 16 14 13 Long-term Years YEAR OF PRODUCTION 2014 2015 2016 2017 2018 2019 2020 DRAM stagger-contacted Metal 1 (M1) ½ Pitch (nm) 28 25 22 20 18 16 14 MPU/ASIC stagger-contacted Metal 1 (M1) ½ Pitch (nm) 28 25 22 20 18 16 14 Flash Uncontacted Poly Si ½ Pitch (nm) 25 23 20 18 16 14 13 MPU Printed Gate Length (nm) 19 17 15 13 12 11 9 MPU Physical Gate Length (nm) 11 10 9 8 7 6 6 The ORTC and technology requirements tables are intended to indicate current best estimates of introduction timing for specific technology requirements. Please refer to the Glossary for detailed definitions for Year of Introduction and Year of Production. TECHNOLOGY PACING In previous editions of the ITRS, the term “technology node” (or “hpXX node”) was used in an attempt to provide a single, simple indicator of overall industry progress in integrated circuit (IC) feature scaling. It was specifically defined as the smallest half-pitch of contacted metal lines on any product. Historically, DRAM has been the product which, at a given time, exhibited the tightest contacted metal pitch and, thus, it “set the pace” for the ITRS technology nodes. However, we are now in an era in which there are multiple significant drivers of scaling and believe that it would be misleading to continue with a single highlighted driver. For example, along with half-pitch advancements, design factors have also rapidly advanced in Flash memory cell design, enabling additional acceleration of functional density. Flash technology has also advanced the application of electrical doubling of density of bits, enabling increased functional density independent of lithography half-pitch drivers. A second example is given by the MPU/ASIC products, for which the speed performance driver continues to be the gate-length isolated feature size, which requires the use of leading-edge lithography and also additional etch technology to create the final physical dimension. Significant confusion relative to the historical ITRS node definition is already reflected in many press releases and other documents that have referred to “node acceleration” based on other, frequently undefined, criteria. Of course, we now expect different IC parameters to scale at different rates, and it is certainly legitimate to recognize that many of these have product-specific implications. Thus, in the 2005 ITRS, we no longer use the term “technology node.” Instead, each distinct scaling feature is specifically referenced as such. Note that, for some degree of continuity, we are still showing DRAM M1 half-pitch at the top of many tables, but it is no longer described as the measure of “technology node.” It is just one among several historical indicators of IC scaling. With this change, it is hoped that the ITRS will no longer contribute to industry confusion related to the concept of “technology node.” Of course, “node” terminology will continue to be used by others. Hopefully, they will define their usage in each case, for example, the metal-1 pitch of their specific product. For reference on the 2005 ITRS common definition of M1 half-pitch for all products, as well as the definition of polysilicon half-pitch for FLASH memory, see Figure 2. 6 Introduction THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 Figure 2 2005 Definition of Pitches MEANING OF ITRS TIME OF INTRODUCTION The ORTC and technology requirements tables are intended to indicate current best estimates of introduction time points for specific technology requirements. Ideally, the Roadmap might show multiple time points along the “research- development-prototyping-manufacturing” cycle for each requirement. However, in the interests of simplicity, usually only one point in time is estimated. The default “Time of Introduction” in the ITRS is the “Year of Production,” which is defined in Figure 3. Figure 3 A Typical Production “Ramp” Curve Volume (Parts/Month) 1K 10K 100K Months 0 -24 1M 10M 100M Alpha Tool 12 24 -12 Development Production Beta Tool Production Tool First Conf. Papers First Two Companies Reaching Production Volume (Wafers/Month) 2 20 200 2K 20K 200K Production Ramp-Up Model and Technology Node Cycl Timing Volume (Parts/Month) Volume (Wafers/Month) Metal Pitch Typical DRAM/MPU/ASIC Stagger-contacted Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Poly Pitch Typical flash Un-contacted Poly FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2 8-16 Lines Introduction 7 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 The “Production” time in the ITRS refers to the time when the first company brings a technology to production and a second company follows within three months. Production means the completion of both process and product qualification. The product qualification means the approval by customers to ship products, which may take one to twelve months to complete after product qualification samples are received by the customer. Preceding the production, process qualifications and tool development need to be completed. Production tools are developed typically 12 to 24 months prior to production. This means that alpha and succeeding beta tools are developed preceding the production tool. Also note that the Production “time zero (0)” in Figure 3 can be viewed as the time of the beginning of the ramp to full production wafer starts. For a fab designed for 20K wafer-starts-per-month (WSPM) capacity, the time to ramp from 20 WSPM to full capacity can take nine to twelve months. This time would correspond to the same time for ramping device unit volume capacity from 6K units to 6M units per month if the chip size were 140 mm2 (430 gross die per 300 mm wafer × 20K WSPM × 70% total yield from wafer starts to finished product = 6M units/month). 2005 SICAS INDUSTRY MANUFACTURING TECHNOLOGY CAPACITY UPDATE It is noted that the ITRS, by its definition, focuses on forecasting the earliest introduction of the leading-edge semiconductor manufacturing technologies, which support the production of selective leading-edge driver product markets, such as DRAM, Flash, MPU, and high-performance ASICs. It is, however, true that many companies, for a variety of reasons, may choose to introduce a leading-edge technology later than the earliest introduction of the leading- edge technology; hence, there is a wide variation of the technologies in actual production status from leading edge to trailing edge. Figure 4 shows, in horizontal bar graph format (normalized by bar area to total MOS IC industry silicon processing capacity), the actual, annual worldwide wafer production technology capacity distributions over different process feature sizes. The distributions of the overall industry technology capacity segments are tracked by feature-size splits, which are quite widespread. The ITRS technology cycle, as measured by DRAM metal 1 (M1) half-pitch, is shown as yellow marks (for the historical actual timing), as reported by the industry surveys conducted by ITRS TWGs. The surveys conducted in 2003 and 2005 have indicated that first production of the leading-edge DRAM M1 half-pitch has been on a two-year cycle (for 0.71× reduction), from 250 nm in 1998 through 90 nm in 2004. The blue mark indicates the timing for the next 2005 ITRS target for the 65 nm technology in 2007. Subsequent targets for 0.71× reduction of the DRAM M1 half-pitch are placed on a three-year cycle through the present ITRS roadmap horizon in 2020. Note that the first production of the leading-edge feature size ramps into a 20–30% industry capacity share within one year, and the timing of that 20–30% capacity share has been on the same cycle as the timing for first production. Furthermore, the relative percentage of the most leading-edge technology capacity has been rapidly growing. The combined capacity of the most recent two technology generations rapidly grows to nearly half the capacity of the industry within two to three years after their introduction. However, it is also notable that relative share of trailing edge capacity does not appear to decline rapidly (migrate upward to leading-edge), and the leading-edge capacity split shares get “crowded” as products migrate to the next leading-edge capacity. This phenomenon has significant implications to the markets and business models of the materials and equipment suppliers that ultimately develop and deliver the required solutions to the ITRS technology “grand challenge.” Suppliers must support not only longer-lasting trailing edge factories, but also many diverse technology factories at the leading edge. In addition, suppliers must deliver alpha and beta tools and materials two to three years ahead of the first production requirement, and then they must be prepared to ramp into production with overlapping technology demand capacities. These scenarios present both a market opportunity and also an R&D and support resource challenge. 8 Introduction THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 Figure 4 Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution1 ROADMAP SCOPE Traditionally, the ITRS has focused on the continued scaling of CMOS (Complementary Metal-Oxide-Silicon) technology. However, since 2001, we have reached the point where the horizon of the Roadmap challenges the most optimistic projections for continued scaling of CMOS (for example, MOSFET channel lengths below 9 nm). It is also difficult for most people in the semiconductor industry to imagine how we could continue to afford the historic trends of increase in process equipment and factory costs for another 15 years! Thus, the ITRS must address post-CMOS devices. The Roadmap is necessarily more diverse for these devices, ranging from more familiar non-planar CMOS devices to exotic new devices such as spintronics. Whether extensions of CMOS or radical new approaches, post-CMOS technologies must further reduce the cost-per-function and increase the performance of integrated circuits. Thus new technologies may involve not only new devices, but also new manufacturing paradigms. Microprocessors, memories and logic devices require silicon-based CMOS technologies. The downscaling of minimum dimensions enables the integration of an increasing number of transistors on a single chip, as described by Moore's Law. The essential functions on such a system-on-chip (SoC) are data storage and digital signal processing. However, many functional requirements, such as power consumption, wireless communication (RF), passive components, sensing and actuating, and biological functions do not scale with Moore’s Law. In many of these cases, non-CMOS solutions are employed. SoC and SiP are not necessarily competing with each other. In the future, the integration of CMOS- and non- CMOS based technologies within a single package (or system-in-package, SiP) will become increasingly important. Furthermore, functions initially fulfilled by non-CMOS dedicated technologies can be in a later step integrated onto a CMOS SoC using mixed technologies derived from core CMOS. So the partitioning of system-level functions between SoC and SiP is likely to be dynamic over time. This will require innovations in cross-disciplinary fields, such as nano- electronics, nano-thermomechanics, nano-biology, etc. For SiP applications, packaging will be a functional element and a key differentiator. Refer to Figure 5 for an illustrative graphic. 1 The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Supply statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2005. The detailed data are available to the public online at the SIA website, http://www.sia-online.org/pre_stat.cfm. Introduction 9 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 Figure 5 Moore’s Law and More The scope of the 2005 ITRS specifically includes detailed technology requirements for all CMOS integrated circuits, including wireless communication and computing products. This group constitutes over 75% of the world's semiconductor consumption. Of course, many of the same technologies used to design and manufacture CMOS ICs are also used for other products such as compound semiconductor, discrete, optical, and micro-electromechanical systems (MEMS) devices. Thus, to a large extent, the Roadmap covers many common technology requirements for most IC- technology-based micro/nanotechnologies, even though that is not the explicit purpose of the Roadmap. POSITION ON POTENTIAL SOLUTIONS The ITRS strives to avoid prematurely identifying definite solutions to the future technology challenges. This is difficult, since guidance on the research needs is intended. Despite this need to provide guidance, the Roadmap participants are continually pursuing new ways to prevent the Roadmap itself from being interpreted as limiting the range of creative approaches to further advance microelectronics technology. One of the resulting compromises has been to only present illustrative examples of potential solutions to selected challenges in the ITRS. These are not to be construed even as complete lists of all solutions suggested to date, much less exhaustive lists of what should be explored. A few of the potential technical solutions are listed, where known, only to inform the readers of current thinking and efforts. Furthermore, the listing of a particular potential solution does not constitute an endorsement by the Roadmap process. It is the intent of this document to identify the technological barriers and when the industry will likely run into them. It is not the intent of this document to identify the most likely solutions to be adopted, nor to focus attention on those potential solutions currently known at the expense of other new concepts. In fact, it is eagerly hoped that this Roadmap will inspire additional innovative solutions. The semiconductor industry’s future success continues to depend on new ideas! 2005 ITRS SPECIAL TOPICS WIRELESS TECHNOLOGY In past years the scope of the ITRS has been widened continuously: In the 2003 version of the ITRS a new sub-chapter on Wireless Technologies was included to take into account that mobile applications have quickly grown to become an More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators HV Power Analog/RF Passives 130nm 90nm 65nm 45nm 32nm 22nm ... V Information Processing Digital content System-on-chip (SoC) Interacting with people and environment Non-digital content System-in-package (SiP) Beyond CMOS More Moore: MiniaturizationMore Moore: Miniaturization Baseline CMOS: CPU, Memory, Logic 10 Introduction THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 important driver for semiconductor products and technologies. The ITRS had therefore been expanded by extending the scope of the already existing analog and mixed-signal (AMS) working group to include radio frequency (RF) technologies for wireless communication and also III-V compound semiconductors in the 2003 ITRS Roadmap as a section in the Process Integration chapter. In the present 2005 ITRS edition, Wireless Technology becomes a separate chapter taking into account the growing importance of this field and its specific performance requirements at the device and system level (low standby power, low operating power). EMERGING RESEARCH DEVICES The 2001 ITRS document marked the additional investigation of the limits of traditional scaling, its extension by improving electrical performance with new or improved materials and of the introduction and feasibility of new device architectures. This new section on Emerging Research Devices (ERD), first presented in 2001 highly coordinated with the Process Integration, Devices, and Structures (PIDS) chapter, has evolved considerably since then. In this 2005 ITRS edition, Emerging Research Materials is now a separate chapter. Some of the new device and memory concepts that were previously discussed in the ERD section have become more mature in the recent years. Therefore these concepts have been transferred from the ERD chapter into the PIDS and Front End Processes (FEP) chapters. This transfer includes the so-called non-classical CMOS devices, both single-gate and multi-gate architectures, as well as the phase-change-memory and the floating-body DRAM. EMERGING RESEARCH MATERIALS Many of the new device and memory concepts that are being discussed in the ERD chapter will employ new materials, for example, for the device itself as well as for interconnect and passivation. The requirements for these new materials are critically dependant on the properties and specifications of the new devices and memories. To support the Technology Working Group of ERD, a sub-group for Emerging Research Materials (ERM) has been formed. The results of this work are published in the Emerging Research Materials (ERM) sub-chapter in the ERD chapter. Grand Challenges 11 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 GRAND CHALLENGES IN THE NEAR- (THROUGH 2013) AND LONG-TERM (2014 AND BEYOND) OVERVIEW The continued research and development efforts in our industry have brought about reacceleration and diversification of scaling, although the 2003 edition of ITRS reported on the deceleration of scaling envisaged by Moore’s Law to a three- year cycle. Flash device’s scaling is still a two-year cycle until 2006, MPU is a 2.5-year cycle until 2010, and DRAM is a three-year cycle. The word “node” cannot define technology trend clearly anymore. In the chapter on PIDS, it is observed that there are many choices to improve MOSFET performance, which we call “Parallel Paths” of planer bulk MOSFET, FD-SOI MOSFET, and Fin-FET. The ITRS is entering a new era as the industry begins to address the theoretical limits of CMOS scaling. There remain many technological challenges to be overcome to achieve continuing growth of the semiconductor industry. Each ITWG identified and listed “Difficult Challenges.” In this section of “Grand Challenges,” major “Difficult Challenges” are selected and described. This section is intended to help readers grasp an overall picture concerning major technological issues. It should be noted there are many other important challenges that are not included in this section. ITRS is rather intended to encourage creative and flexible approaches to advanced microelectronics technologies. These “Grand Challenges” are classified into two categories: “Enhancing Performance” and “Cost-effective Manufacturing.” They are also described according to the “near term” (2005 through 2013) and the “long term” (2014 through 2020) timeframes of the Roadmap. IN THE NEAR TERM (THROUGH ~2013) ENHANCING PERFORMANCE SCALING OF MOSFETS TO HALF PITCH 32 NM [PROCESS INTEGRATION, DEVICES, AND STRUCTURES] Scaling planar bulk CMOS will face significant challenges. The required high-channel doping to control short-channel effects degrades carrier mobility, lowers the drain current, and increases band-to-band tunneling across the junction and gate-induced drain leakage (GIDL). Moreover, statistical fluctuation of channel dopants causes increasing variation of the threshold voltage, posing difficulty in circuit design while scaling the supply voltage. Implementation into manufacturing of new structures such as ultra-thin body, fully depleted silicon-on-insulator (SOI), and multiple-gate MOSFETs (e.g., finFETs) is expected. This implementation will be challenging, with numerous new and difficult issues. A particularly challenging issue is the control of the thickness, including its variability, of these ultra-thin MOSFETs. The solutions for these issues should be pursued concurrently with circuit design and architecture improvements, particularly to manage power dissipation. SIGNAL ISOLATION [RADIO FREQUENCY AND ANALOG/MIXED-SIGNAL TECHNOLOGIES FOR WIRELESS COMMUNICATIONS] Signal isolation, especially between the digital and analog regions of the chip, is a particular challenge for scaled technologies and for increased integration complexity. Noise coupling may occur through the power supply, ground, and shared substrate. The difficulty of integrating analog and high-performance digital functions on a chip increases with scaling in both device geometry and supply voltage. Signal isolation is critical for success in co-integrating high performance analog circuits and highly complex digital signal processing (DSP) functions on the same die or substrate. Such co-integration is required in many modern communication systems to reduce size, power, and cost. HIGH-PERFORMANCE AND LOW-COST RF AND ANALOG/MIXED-SIGNAL SOLUTIONS [RADIO FREQUENCY AND ANALOG/MIXED-SIGNAL TECHNOLOGIES FOR WIRELESS COMMUNICATIONS] Fundamental changes in materials and structures of the low standby power (LSTP) devices will be required to sustain continued performance and density improvement. The introduction of new materials such as high-permittivity (high-κ) gate dielectrics, embedded structures to induce channel strain, and metal-gate electrodes makes predicting trends uncertain for threshold and current mismatch and for 1/f noise. The electrical characteristics of non-classical CMOS, such as dual-gate, fully depleted SOI devices, are fundamentally different than that of conventional CMOS. These differences include benefits for circuit designers as well as obstacles to be overcome. Thus, the fabrication of 12 Grand Challenges THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 conventional precision analog/RF driver devices, resistors, and varactors may require separate process steps with the attendant increase in die cost. Furthermore, the steady reduction in analog supply voltage poses a significant circuit design challenge. NEW GATE STACK PROCESSES AND MATERIALS [PROCESS INTEGRATION, DEVICES, AND STRUCTURES AND FRONT END PROCESSES] Equivalent electrical oxide thickness becomes increasingly thinner due to the requirement for CV/I improvement. Reduction of the equivalent gate oxide thickness (EOT) has emerged as the most difficult challenge associated with the future device scaling. Continued optimization of oxynitride gate dielectric and scaling of this material toward EOT of less than 1 nm consistent with device reliability is envisaged for high-performance (HP) MPU. Oxynitride, however, will no longer meet the strict leakage current requirement in low-power applications (low operating power (LOP) and LSTP). Therefore, introduction of higher dielectric constant (high-κ) material in which tunneling current can be suppressed while maintaining the drain current will be necessary. In either case, the gate electrode material and process should be optimized so that the depletion width in the gate electrode may be minimized and the boron-diffusion prevented. The former necessitates the introduction of metal gates having appropriate work function after the conventional poly Si ceases to work. These material changes pose a great challenge in MOSFET technology, where silicon dioxide/poly Si has long played a central role as the most reliable gate stack system and also these new high-κ and metal gate stacks are fundamental structure expected to be used with the future new structure CMOS such as fully-depleted SOI or multi-gate MOSFETs. CMOS INTEGRATION OF NEW MEMORY MATERIALS AND PROCESSES [FRONT END PROCESSES] Continued DRAM scaling requires construction of memory capacitors in ever-smaller cell area, while maintaining the memory capacitance of 25–35 fF to ensure reliability of stored data. This has resulted in the introduction of dielectric materials with a high dielectric constant (high-κ), such as aluminum oxide, aluminates (for example, HfAlOx) and tantalum oxide, along with a three-dimensional (3D) memory structure. The capacitor structures are shifting from metal- insulator-silicon (MIS) to metal-insulator-metal (MIM) to avoid problems associated with capacitor dielectric thickness. For further scaling, however, it will be necessary to address process construction by using a thinner dielectric film and/or a higher dielectric constant material. In Flash memory devices, on the other hand, continuous scaling and the reduction in write voltage requires the use of a thinner inter-poly and tunnel oxide. Tunnel oxide must be thick enough to assure retention but thin enough to allow ease of erase/write. Inter-poly dielectric must be thick enough to assure retention but thin enough to keep an almost constant coupling ratio. This difficult trade-off problem hinders scaling, suggesting the need to introduce high-κ material and 3D structure devices into Flash memory process. Along with scaling issue of ferroelectric material in FeRAM, process integration of these materials and 3D capacitor will continue to pose major challenges in the development of memory applications. IMMERSION LITHOGRAPHY [LITHOGRAPHY] As a successor to ArF lithography, immersion technology has the potential to extend optical lithography down to 32 nm half pitch, with lesser focus on the other candidates for the post-ArF lithography. To realize immersion lithography in volume production in time it is imperative to ensure its maturity. Control of defects, including bubbles, and staining developed within the immersion environment has been a critical issue in immersion lithography, and improvement of immersion resists and top-coats is required urgently. The proposed line widths are smaller than those for existing ArF lithography, so, as a result, the resist performance requirements for immersion, such as line edge roughness (LER), scanning electron microscope (SEM) induced critical dimension (CD) changes and defects size, are difficult. Moreover, to extend immersion lithography down to 32 nm half-pitch requires development of resist with a very high index of refraction, high index immersion fluid, its recycling system, and higher index lens materials. EUVL: EXTREME ULTRA VIOLET LITHOGRAPHY [LITHOGRAPHY] Although immersion technology shows the possibility of extending optical lithography down to 32 nm half pitch, lithography beyond this is controversial. Candidates for post-optical lithography are extreme ultraviolet lithography (EUVL), mask-less lithography (ML2), and imprint technology. EUVL has noticeably higher throughput than the other candidates, and has the potential to cover from 45 nm to 16 nm half pitches and beyond. In order to introduce EUVL into volume production in time, there are many remaining issues requiring real solutions that must satisfy both technical and economical considerations. These issues include mask blank defect level, light source, resist, optics performance, contamination of optics, protection of mask without pellicle, and so on. Grand Challenges 13 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 CD AND LEFF CONTROL [FRONT END PROCESSES, LITHOGRAPHY AND PROCESS INTEGRATION, DEVICES, AND STRUCTURES] With the aggressive scaling of gate length, control of CD has been one of the most difficult issues in lithography and etching. In particular, resist slimming and profile-control of the sidewall, which are both commonly utilized to minimize the dimension of effective gate length (Leff), have made CD control far more difficult. Although the acceptable 3-sigma variation of the gate length is shared by lithography and etching at an optimum ratio, the tolerances in both technologies are approaching their limits. In addition, it is becoming very difficult to suppress LER, which depends on gate material, photoresist type, and etch chemistry, even by the optimum control of resist printing and etching. CD control and LER measurement also pose challenges to metrology in terms of accuracy and efficiency. Since off-current between source and drain may be affected by the LER, target for controlling LER should be set with understanding the impact of LER on device performance. Moreover, the introduction of new gate materials and non-planar transistor structure requires many more challenges in selective etch processes, and improved anisotropy with the controlled sidewall features. INTRODUCTION OF NEW MATERIALS TO MEET HIGH CONDUCTIVITY AND LOW DIELECTRIC PERMITTIVITY REQUIREMENTS [INTERCONNECT] To minimize signal propagation delay and power consumption, development of low dielectric constant (low-κ) material together with low-resistivity metal system is critical. Low-κ material should have sufficient mechanical/chemical/thermal integrity to survive harsh integration processes, such as chemical mechanical planarization (CMP), etching/ashing/wet cleaning, and assembly/packaging. Since resistivity of narrow Cu interconnect wire is predicted to start to increase below 100 nm line width due to electron scattering at the Cu/barrier-metal interface and the grain boundary, and the influence on circuit performance is becoming serious gradually for intermediate wiring since 65 nm half pitch (circa 2007), care should be taken at 32 nm half pitch (circa 2013). “Barrier engineering” including construction of very thin and low-resistive barrier metal, as well as efficient “pore sealing” for low-κ material, is essential to achieve high conductivity in a narrow Cu interconnect. ENGINEERING MANUFACTURABLE INTERCONNECT STRUCTURES [INTERCONNECT] Introduction of new materials and technologies for interconnect has raised additional issues due to their combinations and interactions. These include adhesion at the interfaces, contamination, diffusion, and leakage concerns. The revealed issues related to mechanical and chemical damage by CMP and etching/ashing/wet process should be solved. Complexity in interconnect structure also makes the effective dielectric constant deviate from its intrinsic value. Failure mechanisms in the Cu/low-κ systems should be clarified, along with establishment of detection metrology and predictive models. In regard to assembly and packaging technology, lack of optimization tools for interconnect/packaging architecture design makes total optimization of interconnect system difficult. MANAGEMENT OF OVERALL POWER CONSUMPTION [DESIGN] Non-ideal scaling of planar CMOS devices, together with the roadmaps for interconnect materials and package technologies, presents a variety of challenges related to power management and current delivery. First, extrapolation from the Overall Roadmap Technology Characteristics and the System Drivers chapter shows that high-performance MPU power consumption significantly exceeds the high-performance single-chip package power limits established in the Assembly and Packaging chapter, even with allowed power densities in excess of 250 W/cm2. The SOC-Power Efficient (PE) driver requires flat or almost flat power, even as logic content (even in the presence of massive multi-processing) and throughput continue to grow exponentially. Design technology (DT) must address the resulting power management gap, which is reiterated in the System Drivers chapter. Additionally, increasing power densities worsen thermal impact on reliability and performance, while decreasing supply voltages worsen switching currents and noise. These trends stress on-chip interconnect resources (such as to control infrared (IR) drop in light of the Assembly and Packaging roadmap for bump count and passivation opening size), automatic test equipment (ATE) limits, and burn-in paradigms. Integration of distinct HP, LOP, and LSTP devices demands power optimizations that simultaneously exploit many degrees of freedom, including multi-Vt, multi-Tox, multi-Vdd inside cores and among cores—while guiding additional power optimizations at the architecture, operating system, and application software levels. HIGH-FREQUENCY DEVICE AND CIRCUIT MODELING FOR 5-100 GHZ APPLICATIONS [MODELING AND SIMULATION] Accurate and efficient modeling of interconnect parasitics and delays is of prime importance. Two-dimensional (2D) and three-dimensional (3D) effects on interconnects must be considered with their statistical variations. Partitioning is needed for distributed R-L-C extractions. Efficient simulation technique should handle multi-layer dielectrics. Compact models are needed for active devices, such as hetero junction bipolar transistors (HBTs), CMOS, laterally diffused (LD) 14 Grand Challenges THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 MOSFETs, and III/V materials. These include non-quasi-static effects, substrate noise, 1/f noise, and surrounding parasitics. Compact models are needed for passive devices (for example, varactors, inductors, high-density capacitors, transformers, and transmission lines). These parameter extractions for RF compact models preferably try to minimize RF measurements. Parameters should be extracted from standard I-V and C-V measurements with supporting simulations, if needed. Modeling of effects that have a more global influence gains importance. Examples are crosstalk, substrate return path, substrate coupling, electromagnetic (EM) radiation, and heating. For these global effects, accurate and efficient layout extractions are needed. If possible, models should be physics-based to enable efficient modeling of statistics and variations. FRONT-END PROCESS MODELING FOR NANOMETER STRUCTURES [MODELING AND SIMULATION] Front-end process modeling for nanometer structures is a key challenge for the prediction of device performance. It overlaps to some extent with the Difficult Challenge of “Ultimate nanoscale CMOS simulation capability,” which also includes material and device simulation. Most important and challenging in the area of front-end process modeling is the modeling of ultra-shallow junction formation, which starts from very low energy implant and especially focuses on the thermal annealing, diffusion and activation of dopants under implantation damage and stress. Due to the strongly reduced thermal budgets needed for shallow junction, the junction formation process is highly transient and is governed by the diffusion and reaction of dopant atoms and defects, and especially by the dynamics of clusters of dopant atoms and defects. Implantation damage, amorphization, recrystallization, and silicidation must be accurately simulated. To meet these requirements, hierarchy approach from atomistic to continuum of dopants and defects are needed. Model development, calibration and evaluation as well as process characterization require numerous experimental activities and large progress in the metrology for dopants, defects and stress, especially regarding two-dimensional and three- dimensional measurements. COST-EFFECTIVE MANUFACTURING SCALING OF MAXIMUM QUALITY DESIGN IMPLEMENTATION PRODUCTIVITY [DESIGN] The number of available transistors double every technology cycle, increasing design complexity as well. In order to maintain design quality even after process technologies advance, design implementation productivity must be improved to the same degree as design complexity is scaled. Improving design productivity and reusing the design are the key considerations for this issue. Namely, overall design productivity of quality- (difficulty-) normalized functions on-chip must improve at the rate of two times per technology cycle. However, analog and mixed-signal design traditionally suffers from difficulty in improving design productivity and reusing the design along with process migration. There is a pressing need to develop a new design methodology to ameliorate those problems by implementing analog and mixed- signal synthesis, verification, and testing. Embedded software productivity also needs to be improved on a similar scale since the on-chip memory size is also growing and some functions are built into such embedded software rather than the hardware. ENABLING TEST OF INCREASINGLY COMPLEX DEVICES [TEST AND TEST EQUIPMENT] Several device trends are presenting great challenges to test. Increasing device IO bandwidth requirements are rapidly driving the proliferation of faster and wider high-speed interfaces. Increasing integration of previously disparate semiconductor technologies in System-On-Chip (SOC) or System-In-Package (SIP) designs are driving significant rethinking of test strategies. Emerging technologies such as RF, analog, optical and MEMs present some unique test challenges and will require significant improvements in test methods as they become more pervasive or integrated with digital CMOS technologies. The increasing variety and complexity of device package designs coupled with an increasing divergence of the electrical/thermal/mechanical characteristics between the end-use and test environments is driving ever more complex and optimized test capability. Finally, several device architecture trends such as more sophisticated power management or self repair mechanisms could lead to new test requirements that depart from the longstanding deterministic stored stimulus and response test model. CONTINUED ECONOMIC SCALING OF TEST [TEST AND TEST EQUIPMENT] The ever-improving economies of scale predicted by Moore’s Law do not translate to test. Design For Test (DFT) innovations, widespread use of structural test techniques such as scan testing, and the enabling of higher levels of test parallelism have been very successful in keeping test costs in check to date. However, new test requirements for increasingly complex devices, increasing quality requirements and practical limits on parallel testing will present great challenges in the future. In particular, some contributors to the total cost of test, such as test tooling (e.g., probe cards), are not scaling and threaten to dominate the total test cost if present trends continue. Grand Challenges 15 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 INCREASING TEST PROCESS COMPLEXITY [TEST AND TEST EQUIPMENT] Process complexity is both a grand challenge and an opportunity for test. The value proposition of test has been steadily increasing as semiconductor manufacturers attempt to get more and more out of test. Increasingly, test is used to modify, differentiate, or customize specific die. Increasingly sophisticated data feedback is being used to tune manufacturing. Test for yield learning is already critical and this is expected to become more so with the introduction of new semiconductor processes that will be inherently more variable. Increasing device complexities are also leading to a higher order dimensionality of test conditions (for example, adding multi-power, multi-voltage, multi-frequency topologies as opposed to single valued temperature, voltage and frequency). RESPONDING TO RAPIDLY CHANGING COMPLEX BUSINESS REQUIREMENTS [FACTORY INTEGRATION] Various types of business models such as integrated device manufacturer (IDM), collaboration between fabless and foundry, joint venture, and variety of task sharing and out-sourcing have emerged and become widespread in response to customers’ rapidly changing complex business requirements. It is noteworthy that a high-mix and low-volume manufacturing model is in a strong demand in response to diversified customers’ requirement on SoC devices. Semiconductor manufacturing factories now must integrate and implement an even larger number of new and different capabilities in factory integration technology regime in a much shorter time and cost effective manner. The ultimate goal for this is to realize high product reliability and productivity in volume manufacturing or in the high mix and small volume-manufacturing model. Development of information exchange/control platform covering all the relevant operation fields, extending from design, mask, front-end-of-line (FEOL), and back-end-of-line (BEOL) to testing, packaging, etc., is also a crucial challenge. Modeling of factory capacity detailed with various parameters and metrics is the base requirement for more comprehensive and integrated factory operation decisions to be made for the necessary optimization among product cycle time, product reliability, and the productivity. It is fundamentally required to establish an information platform on which more abstraction of problems and requirements with the finer granularity of information is to be performed. The Factory Integration chapter is to be referred for “Proactive Visualization” and “Strategically Hierarchical Quality Assurance.” IMPROVEMENT IN TRADE-OFF BETWEEN MANUFACTURING COST AND CYCLE TIME [FACTORY INTEGRATION] It is well known that cost and the manufacturing cycle time are in a trade-off relation among other Factory Integration problems. Job flow manufacturing and single-wafer manufacturing methods have been investigated to improve this problem. The grand premise for these manufacturing methods to be applied is the much higher availability, stability and reliability of the process tools and elimination of non-product wafers (NPW) processing and tool set up operations. This premise is becoming more difficult to be assumed as manufacturing needs go into the more stringent process rules. This fundamental improvement cannot be achieved by the individual productivity improvement effort by each of the device makers, but it calls for the industry’s reformation including revised task sharing where the collaborative efforts are required based on an equipment engineering system (EES) scheme. The implementation of enhanced equipment quality assurance (EEQA) is an immediate challenge as the very first step of this improvement where equipment suppliers are to use an EES scheme to examine equipment capabilities with electronic data out of equipment. MEET THE CHANGING COST AND PERFORMANCE REQUIREMENT OF THE MARKET [ASSEMBLY AND PACKAGING] Many new materials will be introduced in IC packages in next few years in order to meet requirements of environmental regulations, to improve package performance, and to be compatible with low-κ dielectrics used in Cu interconnects with 65 nm half pitch and beyond. Nano-materials present significant opportunities that the packaging community needs to take advantage of. The ICs front-end progress is based upon a high level of investment in material and process technology and equipment. There is no corresponding investment in the back-end for materials, process, and equipment. Wafer-level package and SiP have promises of dramatic cost performance and form factor improvement. The industry will require investment and knowledge of infrastructure to perfect technology of high-volume production. The changing marketplace by consumerization of electronic products presents the tremendous opportunity for the packaging industry in implementing the technologies to fill the gap created by physical limit of Moore’s law scaling. CHEMICAL AND MATERIAL ASSESSMENTS [ESH] The rapid introduction of new chemicals, materials, and processes requires new rapid assessment methodologies to ensure that new chemicals and materials can be utilized in manufacturing without inducing new hazardous impacts on human health, safety, and the environment. Although methodologies are needed to meet the evaluation and quantification demands for ESH impacts, the focus is currently on expediting process implementation. 16 Grand Challenges THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2005 RESOURCE CONSERVATION [ESH] As the industry grows and its technology advances toward finer patterning and larger wafer sizes, the natural tendency is toward increased use of water, energy, chemicals, and materials. Resource conservation is becoming a major concern with respect to availability, cost reduction, manufacturing location, sustainability, and waste disposal. Thus, it is necessary to develop diverse process equipment capable of utilizing resources efficiently. SIGNAL TO NOISE RATIO [YIELD ENHANCEMENT] Currently inspection systems are expected to detect defects of sizes scaling down in the same way or even faster as feature sizes required by technology cycles. Increasing the inspection sensitivity at the same time increases the challenge to find small but yield-relevant defects under a vast amount of nuisance and false defects. At the same time a low cost of ownership (CoO) of the tools is demanded for high throughput inspection. This is in conflict with the issue of improving the signal-to-noise ratio. The key of a successful inspection result is, besides achieved sensitivity, the ease to get to the defects of interest (DOI). HIGH THROUGHPUT LOGIC DIAGNOSIS CAPABILITY [YIELD ENHANCEMENT] The irregularity of features makes logic areas very sensitive to systematic yield loss mechanisms such as patterning marginalities across the lithographic process window. Before reaching random-defect limited yields, the systematic yield loss mechanisms should be efficiently identified and tackled through logic diagnosis capability designed into products and systematically incorporated in the test flow. Potential issues can arise due to different automatic test pattern generation (ATPG) flows accommodation; ATE architecture that lead to significant test time increase when logging the number of vectors necessary for the logic diagnosis to converge, and logic diagnosis run time per die. WAFER EDGE AND BEVEL CONTROL AND INSPECTION [YIELD ENHANCEMENT] Defects and process problems around wafer edge and wafer bevel can cause yield problems. Currently, the defect inspection of the wafer edge and the bevel, as well as the wafer backside, is not paid too much attention. Therefore, the defect inspection concepts or technologies are under development or have to be realized within the next years. It is a key challenge to find the root cause inspection of wafer edge, bevel, and apex on the wafer front and backside. FACTORY LEVEL AND COMPANY WIDE METROLOGY INTEGRATION [METROLOGY] Metrology and combination of metrology for complement should be carefully chosen and sampling must be statistically optimized for process control based on cost of ownership (CoO). On the other hand in situ and inline metrology is becoming requisite for both tight process control and throughput. Information from all metrology (i.e., online and offline metrology), associated with advanced process control (APC), fault detection and classification (FDC), and other systems should be integrated into a database useful for determining process control parameters and correlating metrology information and yield to enhance yield. Therefore, standards for process controller and data management must be agreed upon and the structure of such a database should be optimized. Sensors, their calibration, sensing method, and data processing are being improved and require continued improvement for precise methodology. MEASUREMENT OF COMPLEX MATERIAL STACKS [METROLOGY] Even measurement of film thickness of complex material stacks is difficult for processing wafers. The characterization of complex material stacks and interfacial properties, including physical and electrical properties, is challenging. Direct measurement of stress in a nano-sized and buried area is required. At the same time, reference materials and standard measurement methodologies are critically required for new, high-κ gate and capacitor dielectrics with engineered thin films and interface layers; interconnect barrier and low-κ dielectric layers, as well as other process needs. Carrier mobility characterization will be needed for stacks with strained silicon and SOI substrates. The same is true for measurement of barrier layers. Metal gate work function characterization is another pressing need. IN THE LONG TERM (~2014 THROUGH 2020) ENHANCING PERFORMANCE IMPLEMENTATION OF ADVANCED, NON-CLASSICAL CMOS DEVICE WITH ENHANCED DRIVE CURRENT [PROCESS INTEGRATION, DEVICES, AND STRUCTURES] To continue MOSFET scaling to less than Lg = 15 nm, it is quite likely that the device structure will change to advanced non-classical CMOS such as multiple-gate, ultrathin body (UTB) MOSFETs. In these devices, various “technology boosters,” such as mobility enhancement by strained Si, elevated source source/drain, high-κ gate dielectric, and metal gate electrode, will likely be simultaneously implemented with the new device structure. In UTB MOSFETs having less