Aldec Awarded 2010 Best FPGA Development
Tool in China
September 07, 2010 06:08 AM Eastern Daylight Time
HENDERSON, Nev.--(EON: Enhanced Online News)--Aldec, Inc., a leader in mixed RTL simulation and
verification, announces that Active-HDL was awarded the 2010 Best FPGA Development Tool by the Ministry of
Industry and Information Technology of the People’s Republic of China. The award was presented at the Ministry's
annual FPGA Industry Development Forum on August 31, 2010. The Ministry of Industry and Information is the
governing body responsible for development, coordination, regulation, and standardization of the semiconductor
industry in China.
The award recognized Active-HDL as the superior choice for FPGA designers in China based on its powerful,
easy-to-use FPGA design creation, project management and mixed VHDL and Verilog verification. Years of
customer feedback makes Active-HDL an environment that is comfortable for both beginners and power users.
Close co-operation with leading FPGA vendors ensures seamless integration with vendor tools and full support for
the latest FPGA chip families and technologies
The forum honored the following companies or products:
Active-HDL is an integrated FPGA design and verification environment with a powerful mixed-language simulator
and tools for graphical design entry, project management, HDL verification and documentation, providing an efficient
(FPGA vendor-independent) environment for end-to-end design processing. A multi-vendor flow manager controls
simulation, synthesis and implementation for all devices from all leading FPGA vendors. A co-simulation interface to
MATLAB® and Simulink® facilitates designs with DSP. HDL language support: VHDL, Verilog, EDIF, SystemC
and SystemVerilog. Operating system support: Windows® XP, Vista and 7.
Aldec, Inc., is an industry-leader in Electronic Design Verification and offers a patented technology suite including:
RTL Design, RTL Simulators, Hardware-Assisted Ve