ECSI Institute Workshop
September 13, 2004 – 9:00-18:40 – MACC, Lille, France
The successful usage of Hardware Description Languages like VHDL and Verilog in the design flow is mainly due
to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized
gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of
abstraction despite the failure of previous attempts to behavioural synthesis from higher-level HDL descriptions.
High-level languages like SystemC or SystemVerilog that offer advanced modelling techniques and verification
methods and tools based on them are in progress to enable more efficient verification process. But in order to
provide the designers with an efficient automated path to implementation some kind of system synthesis is
Some automated approaches are nowadays proposed by industry and research to replace the manual recoding of
high-level models into synthesize-able / implementable models:
• automated behavioural synthesis from higher abstraction levels
translation of high-level models (e.g. in SystemC) to HDL RTL models and synthesis
The main expectations from the systems’ industry concern methods and tools supporting better management of the
design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of
various design implementation options. Designing at higher levels of abstraction is an obvious direction as it allows
to better manage the system design complexity, to verify earlier in the design process with higher performance and
to increase IP reuse.
Thus, users formulate several crucial questions with regard to system synthesis:
Is the so called “behavioural synthesis” an appropriate and efficient solution to get to the implementation?
Is it optimal (the RTL optimized, targeted to downstream synthesis tools)?
• What benefit can users gain and at what price: how does it