BHATT DV
Chapter 15 IA-64 Architecture
Motivation
General Organisation
Predication, Speculation, and Software Pipelining
IA-64 Instruction Set Architecture
Itanium Organisation
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Background to IA-64
Pentium 4 appears to be last in x86 line
New approach to provide instruction-level parallelism not
superscalar
Intel & Hewlett-Packard (HP) jointly developed the new architecture
and called it IA-64
64 bit architecture
Not extension of x86
Not adaptation of HP 64bit RISC architecture
Exploits vast circuitry and high speeds of microchips
Systematic use of parallelism
Departure from superscalar
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Motivation
Basic concept of IA-64 are
Instruction level parallelism
Explicit in the machine instruction
Not determined at run time by processor
Long or very long instruction words (LIW/VLIW)
Branch predication (not the same as branch prediction)
Speculative loading
Intel & HP call this Explicit Parallel Instruction Computing (EPIC)
IA-64 is an instruction set architecture intended for implementation
on EPIC
Itanium is first Intel product
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Superscalar v IA-64
Speculatively loads data before its
needed, and still tries to find data in
the caches first
Loads data from memory only when
needed, and tries to find the data in
the cache first
Speculative execution along both
paths of a branch
Branch prediction with speculative
execution of one path
Reorders and optimise instruction
stream at compile time
Reorders and optimise instruction
stream at run time
Multiple parallel execution units
Multiple parallel execution units
RISC-line instructions, bundled into
groups of three
RISC-line instructions, one per word
IA-64
Superscalar
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Why New Architecture?
Not hardware compatible with x86
Now have tens of millions of transistors available on chip
Could build bigger cache
Diminishing returns
Add more execution units
Increase superscaling
“Complexity wall”
More units makes processor “wider”
More logic neede