The products described in this document are PowerPC™ microprocessor cores. This
application note outlines differences between the register models defined by the
Apple/IBM/Freescale (AIM) and Book E versions of the PowerPC architecture and the
registers implemented in the MPC603e processor and the e500 microprocessor core.
Section 1, “Migrating from PowerPC AIM Architecture to Book E Register Model” 2
Section 2, “Special-Purpose Registers by SPR Number”
Section 3, “Special-Purpose Registers by SPR Abbreviation”
Section 4, “Architecture-Defined Non-SPR Registers by Abbreviation”
Section 5, “EIS-Defined Performance Monitor Registers (PMRs)”
Registers defined by the AIM version of the PowerPC architecture are identified by the level
of the architecture at which the register is defined, as follows:
Book I, user instruction set architecture (UISA)
Book II, virtual environment architecture (VEA)
Book III, operating environment architecture (UISA)
Registers defined by the Freescale Book E implementation standards are identified as EIS.
This document does not attempt to identify specific
differences between register fields implemented in a register.
For example, although most machine state register (MSR)
fields are the same in all processors, each device typically
has implementation-specific fields that are not identified in
this document. Consult the user’s manuals for full
descriptions of register fields.
Rev. 0, 7/2003
MPC603e and e500
Register Model Comparison
Freescale Semiconductor, I Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...conductor, Inc., 2004. All rights reserved.
MPC603e and e500 Register Model Comparison
Migrating from PowerPC AIM Architecture to Book E Register Model
1 Migrating from PowerPC AIM Architecture to Book E
Migrating from the PowerPC AIM register model implemen