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Description The CXA1898Q is an IC developed for analog signal processing in tape recorders. Processing for both the recording and playback systems is achieved on one chip. Features • Recording equalizer Gp and Fp can be adjusted externally. • Recording mute function • AGC (Automatic Gain Control) • Comparator for AMS (Automatic Music Sensor) • Recording/playback equalizer amplifier with 1.7 times speed switching • 11-bit serial data interface Absolute Maximum Ratings • Supply voltage VCC 12 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 735 mW Operating Conditions Supply voltage VCC 6.5 to 10.0 V Structure Bipolar silicon monolithic IC Applications All analog signal processing in the cassette decks of tape recorders and compact music centers (Applicable to Sankyo Seiki mfg. Co., Ltd. YK47R-KF202 R/P head or equivalent) – 1 – CXA1898Q E94329B78 Recording/Playback Equalizer Amplifier Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin QFP (Plastic) – 2 – CXA1898Q Block Diagram and Pin Configuration (Top View) IREF PB OUT2 PB FB22 PB FB12 PB INB2 PB INA2 PB INA1 PB INB1 PB FB11 PB FB21 PB OUT1 AMS GAIN CLK LATCH M2 M1 PL2 PL1 BPB BPA PB MUTE SPEED R MUTE2 R MUTE1 MUTEIREFPBEQCTLRECEQCTLRECEQSHIFT REGISTERSGND AGCRECEQ10k 40k 10k 40k AGC GAIN 19.5dBGND GND GND 210k 210k 70k 70k 70k 70k 210k 210k AMS AMS FILAMS OUTAMS GNDFP CALGP CALAGC IN1REC IN1AGC OUT1REC OUT1A EQB EQRMUTE1 IGND GND GND GND GND GND GND GND GND GND GND GND D11 D11 D9 D7 D6 D5 D4 D3 D2 D1 D8 D10 D9 DECK A/B D10 SPEED D9 B EQ A EQ AGC OFF D8 SPEED B EQ AGC GAIN 19.5dBRFCVCCVGGNDAGC TCAGC IN2REC IN2AGC OUT2REC OUT2D GNDXRESETDATAGND GND GND GND GND GND GND 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 25 26 27 28 29 30 36 35 34 31 32 33 14 15 16 17 18 19 20 21 22 23 24 13 LATCHES – 3 – CXA1898Q Pin Description Pin No. 6 31 Symbol DC voltage I/O Equivalent circuit Description AGC IN1 AGC IN2 4.0V I AGC signal input. Input resistance changes between 47kΩ and 3kΩ I/O resistance 50kΩ VCC 147 3k 47k × 4 VCC GND VGS 6 31 7 30 REC IN1 REC IN2 4.0V I Recording equalizer input. 50kΩ 8 29 AGC OUT1 AGC OUT2 4.0V O AGC output pin. AGC is applied at –11dBm or more. 147Ω 9 28 REC OUT1 REC OUT2 4.0V O Recording equalizer output. 147Ω 7 30 VCC 147 50k VCC GND VGS 23k 1.8k VGS GND 8 29 VCC 147 18.8k 500 × 4 VCC GND VGS GNDGND × 2 47.8k 5.3k 500 VGS 9 28 VCC 147 40k 500 × 10 VCC GND GND × 3 500 × 2 5p – 4 – CXA1898Q 10 A EQ — I A deck equalizer switch. Low: 120µs EQ High: 70µs EQ — 10 VCC 147 GND GND VCC 11 B EQ 2.5V (when open) I B deck equalizer switch. Low: Normal Tape, 120µs EQ High: CrO2 Tape, 70µs EQ Medium: Metal Tape, 70µs EQ 53kΩ 12 RMUTE1 I — I Recording mute ON/OFF switch. Low: Mute OFF High: Mute ON ∗ Fader function is realized by the external time constant circuit. Connects Pin 13 (RMUTE1). — 13 14 R MUTE1 R MUTE2 15 SPEED 16 PB MUTE 5.0V (when reset) (when Pin 25 (DATA) is set to high) O Output for recording mute ON/OFF switch control signal. Outputs D11 from Pin 25 (DATA). Output for recording/ playback equalizer speed switch control signal. Outputs D9 from Pin 25 (DATA). Low: Normal Speed High: High Speed (1.7 times) Output pin for playback mute ON/OFF switch control signal. Outputs D7 from Pin 25 (DATA). Connects a resistor to VDD for Pins 13 to 16. — VCC 147 50k VCC GND GND 5k 5k 11 × 2 12 VCC 147 GND GND VCC 20k × 2 20k 2.7V 50µA 14 15 16 × 4 VDD 5k GND GND VCC × 4 5k 13 20k Pin No. Symbol DC voltage I/O Equivalent circuit Description I/O resistance – 5 – CXA1898Q 17 BPA 5.0V (when reset) (when Pin 25 (DATA) is set to high) O Outputs D6 from Pin 25 (DATA). 18 BPB Outputs D5 from Pin 25 (DATA). 19 PL1 Outputs D4 from Pin 25 (DATA). 20 PL2 Outputs D3 from Pin 25 (DATA). 21 M1 Outputs D2 from Pin 25 (DATA). 22 M2 Outputs D1 from Pin 25 (DATA). — × 4 VDD GND GND VCC × 4 10k 20k 17 18 19 20 21 22 23 LATCH 26 XRESET — I Serial data interface latch input. Serial data interface reset input. Low: Reset. At this time serial data outputs (Pins 13 to 22) are all open (high). — 32 AGC TC 0.0V — Connects a resistor and capacitor for determining AGC attack/recovery time constants. — 2k GND VCC 10.5k 25µA 23 26 GND 100µA 24k 5p × 4 24 25 4k GND VCC 10.5k 25µA GND 100µA 24k × 4 32 VCC GND GND VCC × 2 200 100k 500 500 × 2 147 × 2 × 4 200 5k 24 CLK 25 DATA — I Serial data interface clock input. Serial data interface serial data input. — Pin No. Symbol DC voltage I/O Equivalent circuit Description I/O resistance – 6 – CXA1898Q 34 VG 4.0V — Signal reference voltage. Connects a capacitor for ripple rejection. 60kΩ 34 VCC 147 45k 30k × 4 VCC GND GND 500 500 × 2 30k × 2 To each VSG 35 VCC 8.0V — Power supply. — 36 RFC 8.0V — Connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected. — 38 47 PB OUT2 PB OUT1 2.8V O Playback equalizer output. 147Ω 35 VCC 36 VCC 147 VCC GND × 3 × 250 × 3 To each RFS 38 47 VCC 147 5k VCC GND GND × 2 × 3 × 2 × 6 500 500 5p Pin No. Symbol DC voltage I/O Equivalent circuit Description I/O resistance – 7 – CXA1898Q 39 46 PB FB22 PB FB21 2.8V — Connects a capacitor for determining playback equalizer time constants, such as 120µs and 70µs. — 39 46 VCC 147 × 3 GND 2k 2k GND GND × 4 7k × 3 × 4 RFS 40 45 PB INB2 PB INA2 PB INA1 PB INB1 1.4V — Playback equalizer negative feedback. 105kΩ 41 42 43 44 0.0V I Playback equalizer input. 70kΩ 48 AMS GAIN 3.5V — Connects a resistor for determining AMS signal detection level and a capacitor for determining HPF cut-off frequency. — 40 41 42 43 44 45 70k 5p VCC 147 GND VCC GND × 6 VCC GND 1k 1k 210k 210k 147 VCC RFS × 2 10k 10k × 6 48 VCC 147 GND VCC GND 100k 10µ PB FB12 PB FB11 Note) The resistance of open collector outputs (Pins 2 and 13 to 22) can be also connected to VCC. Pin No. Symbol DC voltage I/O Equivalent circuit Description I/O resistance – 8 – CXA1898Q Electrical Characteristics (Ta = 25°C, VCC = 8.0V, VDD = 5.0V, refer to Electrical Characteristics Measurement Circuit) Item Operating voltage Current consumption AGCMeasurement conditions Min. Typ. Max. Unit AMSPlaybackequalizeramplifierblockVCC NORM–NS, VCC = 8V, No signal Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = –25dBm Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = –15dBm Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = 0dBm Pin 32 external R300kΩ/ /C 47µF f = 1kHz, Vin = –25dBm Pin 48 external R9.1kΩ, C0.015µF Pin 1 external R100kΩ/ /C0.1µF f = 5kHz, 0dB = –21dBm (at PBEQ reference output level) f = 315Hz, Vin = –70dBm Reference for frequency response f = 2.7kHz, Vin = –58.5dBm at 120µs–NS, 315Hz f = 4.5kHz, Vin = –53.8dBm at 120µs–NS, 315Hz f = 5.3kHz, Vin = –52.5dBm at 120µs–NS, 315Hz f = 9.1kHz, Vin = –47.8dBm at 120µs–NS, 315Hz 120µs–NS, RL = 2.7kΩ f = 1kHz, THD + N = 1% 120µs–NS, RL = 2.7kΩ f = 1kHz, Vin = –56.4dBm 120µs–NS, Rg = 2.2kΩ "A" weighting filter 120µs–NS, Rg = 70kΩ AGC ON output level AGC ON channel balance AGC ON distortion AGC OFF output level No signal detection threshold level 120µs–NS frequency response 120µs–NS frequency response 70µs–NS frequency response 120µs–HS frequency response 70µs–HS frequency response Signal handling Total harmonic distortion S/N ratio Output offset voltage 6.5 13.5 –13.0 –2.0 — –7.5 –11.5 –23.0 –0.1 –0.1 1.8 2.1 –10.0 — 55.0 2.4 8.0 18.0 –11.0 0.0 0.3 –5.5 –8.2 –21.0 1.3 1.7 3.0 3.6 –6.0 0.3 62.0 2.7 10.0 22.5 –9.0 2.0 1.5 –3.5 — –19.0 2.9 2.9 4.8 5.1 — 0.7 — 3.2 V mA dBm dB % dBm dB dBm dB dBm % dB V – 9 – CXA1898Q dB –26.4 — 1.5 1.1 7.3 16.4 4.2 9.7 18.2 5.7 8.9 15.8 1.7 12.3 19.5 6.0 16.0 22.5 7.3 14.0 19.7 –27.9 –10.0 0.0 –0.2 5.7 13.4 3.0 8.4 15.8 4.5 7.4 13.7 0.2 10.5 16.7 4.9 14.2 20.0 6.1 12.4 17.4 NORM–NS, 315Hz, input level at which reference output can be obtained NORM–NS, 315Hz NORM-NS, 315Hz, Output difference 1ch–2ch for –27.9dBm input f = 3kHz at NORM–NS, 315Hz, reference output –20dB f = 8kHz at NORM–NS, 315Hz, reference output –20dB f = 12kHz at NORM–NS, 315Hz, reference output –20dB f = 3kHz at NORM–NS, 315Hz, reference output –20dB f = 8kHz at NORM–NS, 315Hz, reference output –20dB f = 12kHz at NORM–NS, 315Hz, reference output –20dB f = 3kHz at NORM–NS, 315Hz, reference output –20dB f = 8kHz at NORM–NS, 315Hz, reference output –20dB f = 12kHz at NORM–NS, 315Hz, reference output –20dB f = 5kHz at NORM–NS, 315Hz, reference output -20dB f = 15kHz at NORM–NS, 315Hz, reference output –20dB f = 20kHz at NORM–NS, 315Hz, reference output –20dB f = 5kHz at NORM–NS, 315Hz, reference output –20dB f = 15kHz at NORM–NS, 315Hz, reference output –20dB f = 20kHz at NORM–NS, 315Hz, reference output –20dB f = 5kHz at NORM–NS, 315Hz, reference output –20dB f = 15kHz at NORM–NS, 315Hz, reference output –20dB f = 20kHz at NORM–NS, 315Hz, reference output –20dB –29.4 — –1.5 –1.3 3.7 10.4 1.8 6.7 13.2 3.3 5.9 11.3 –0.7 8.3 13.5 3.6 12.0 17.0 4.9 10.5 14.7 Reference input level Reference output level Channel balance NORM–NS frequency response NORM–NS frequency response NORM–NS frequency response CrO2–NS frequency response CrO2–NS frequency response CrO2–NS frequency response METAL–NS frequency response METAL–NS frequency response METAL–NS frequency response NORM–HS frequency response NORM–HS frequency response NORM–HS frequency response CrO2–HS frequency response CrO2–HS frequency response CrO2–HS frequency response METAL–HS frequency response METAL–HS frequency response METAL–HS frequency response RecordingequalizeramplifierblockItem Measurement conditions Min. Typ. Max. Unit dBm – 10 – CXA1898Q Item RecordingequalizeramplifierblockMeasurement conditions Min. Typ. Max. Unit NORM–NS, RL2.7kΩ f = 1kHz, THD = 1% NORM–NS, RL2.7kΩ f = 1kHz, 0dB NORM–NS, Rg = 5.1kΩ "A" weighting filter NORM–NS NORM–NS, f = 1kHz 8dB, Pin 12 = 3.5V NORM–NS, f = 1kHz 8dB, Pin 12 = 2.0V A-EQ (Pin 10) A-EQ (Pin 10) B-EQ (Pin 11) B-EQ (Pin 11) B-EQ (Pin 11) RMUTE1-I (Pin 12) RMUTE1-I (Pin 12) Signal handling Total harmonic distortion S/N ratio Output offset voltage Mute characteristics 1 Mute characteristics 2 8.0 — 57.0 3.6 — –8.3 0.0 2.5 0.0 2.2 4.2 0.0 3.5 8.8 0.2 60.6 4.0 –100 –7.0 — — — — — — — — 0.5 — 4.4 –80 –4.3 0.5 VCC 0.5 2.8 VCC 0.5 VCC dB % dB V Control voltage low level 1 Control voltage high level 1 Control voltage low level 2 Control voltage medium level 1 Control voltage high level 2 Control voltage low level 3 Control voltage high level 3 Note) NORM–NS : NORMAL TAPE–NORMAL SPEED NORM–HS : NORMAL TAPE–HIGH SPEED CrO2–NS : CrO2 TAPE–NORMAL SPEED CrO2–HS : CrO2 TAPE–HIGH SPEED METAL–NS : METAL TAPE–NORMAL SPEED METAL–HS : METAL TAPE–HIGH SPEED 120µs–NS : EQ = 120µs–NORMAL SPEED 120µs–HS : EQ = 120µs–HIGH SPEED 70µs–NS : EQ = 70µs–NORMAL SPEED 70µs–HS : EQ = 70µs–HIGH SPEED dB V – 11 – CXA1898Q Item 11-bitserialdatainterfaceblockMeasurement conditions Min. Typ. Max. Unit VIL (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26) VIH (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26) VOL, IOL = 2mA (max) (Pins 13, 14, 15, 16, 17, 18, 19, 20, 21, 22) IOZ Leak current which flows to the output pin when Ioz output is open; applied voltage is 10V. (1) fCK (2) tWC (3) tWR (4) tSDK (DATA → CLK) (5) tHCD (CLK → DATA) (6) tWD (7) tSLD (LATCH → DATA) (8) tHCL (CLK → LATCH) (9) tHLC (LATCH → CLK) Low level input voltage High level input voltage Low level output voltage High level output off- leak current Maximum clock frequency Minimum clock pulse width Minimum reset pulse width Minimum data setup time Minimum data hold time Minimum data pulse width Minimum latch setup time Minimum latch hold time Minimum clock hold time 0.0 3.5 0.0 — 500 — — — — — — — — — — — — — — — — — — — — — 1.5 VDD 0.5 1.0 — 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 Note) • VDD is CPU supply voltage 5.0V. • The maximum value for VDD is Pin 35 (VCC) voltage. • For high level output off leak current, VCC is 10.0V. µs V µA kHz – 12 – CXA1898Q Timing Chart for 11-bit Serial Data Interface tWC tWC tWD tHCD tSDK 1.5V 3.5V D1 D2 1.5V 3.5V 1.5V tSLD 3.5V 1.5V 3.5V 1.5V tHCL D10 D11 tHLC tWR CLK DATA LATCH CLK DATA LATCH XRESET – 13 – CXA1898Q Electrical Characteristics Measurement CircuitAM S F IL A M S O U T AM S G N D F P C A L G P C A L A G C IN 1 R E C IN 1 A G C O U T 1 R E C O U T 1 A E Q B E Q R M U T E 1 I CXA1898Q141516171819202122232413234567891011121R F C V C C V G G N D AG C T C AG C IN 2 R E C IN 2 A G C O U T 2 R E C O U T 2 D G N D X R E S E T D A T A 252627282930363534313233403938374142434445464748IREFPB OUT2PB FB22PB FB12PB INB2PB INA2PB INA1PB INB1PB FB11PB FB21PB OUT1AMS GAIN1 0 k 0 .1 µ 1 0 k 0 .1 µ 1 0 k 0 .1 µ 2 .2 µ 4 .7 µ 0 .4 7 µ 0 .4 7 µ 2 .7 k 1 0 k 5 .1 k 5 .1 k 0 .1 µ S 7 F S 1 2D S 2 0 2 7 k 2 7 k 1 0 0 k 4.2V2.0V2.5V3.5V5.0V0.5VS 3 9 S 1 8B 1 0 0 S 2 2A S 2 2B 1 0 k 1 0 0 S 1 6 1 0 k S 1 4B 1 0 k S 2 5 S 2 6 S 2 4 S 2 3 S 2 7 S 2 8A R E C M U T E S 2 8B O N O F F M E T A L C rO 2 N O R M B E Q A E Q 1 2 0 µ s 7 0 µ s S 1 8A 4 7 k 3 9 0 k 0.1µ0.47µS7DS112.2k377k0.1µ0.47µS7CS102.2k377k0.1µ0.47µS7BS92.2k377k0.1µ0.47µS7AS82.2k377k10047µ9.1k2.2µ2.7kS12B0.015µ0 .0 1 8 µ S 1 4A 1 0 0 10047µ0 .0 1 8 µ 2.2µ2.7kS12A12k0 .1 µ S 1 2C 1 0 µ 1k0 .1 µ 1 0 µ 1 0 µ 4 7 µ 3 0 0 k 5 .1 k 2 .7 k 0 .4 7 µ 0 .4 7 µ 4 .7 µ 2 .2 µ 5 .1 k S 7E 0 .1 µ 1 0 k S 1 9 S 1 7A 4 7 k 3 9 0 k 8.0VS 1 5 1 0 k S 1 3B 1 0 k S 1 3A 1 0 0 S 1 7B 1 0 0 S 2 1A 1 0 0 S 2 1B 1 0 k X R E S E T D A T A CLKLATCHS3810k2k1 0 0 k 0 .1 µ S3710k2kS3610k2kS3510k2kS3410k2kS3310k2kS3210k2kS3110k2kS3010k2kS2910k2kDC OUTPUTGNDGNDS501S502S503S504S505AC OUTPUT1 0 0 k BUF30dB AMP"A" Weighting FilterAudio (22.2Hz-22.2kHz) Filter1kHz Band Pass Filter (20dB)TL072GND6 0 0 ATT–6dBS1BS1AATT–9dBS3BS3AATT–17dBS6BS6AATT–29dBS4BS4AATT–40dBS2BS2AAC INPUTCLKLATCHM2M1PL2PL1BPBBPAPB MUTESPEEDR MUTE2R MUTE1 – 14 – CXA1898Q Application Circuit IREF PB OUT2 PB FB22 PB FB12 PB INB2 PB INA2 PB INA1 PB INB1 PB FB11 PB FB21 PB OUT1 AMS GAIN CLK LATCH M2 M1 PL2 PL1 BPB BPA PB MUTE SPEED R MUTE2 R MUTE1 MUTEIREFPBEQCTLRECEQCTLRECEQLATCHES47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k GND 47k SHIFT REGISTERSGND AGCRECEQ10k40k 10k40k AGC GAIN 19.5dBGND GND GND 210k 210k 70k 70k 70k 70k 210k 210k AMS AMS FILAMS OUTAMS GNDFP CALGP CALAGC IN1REC IN1AGC OUT1REC OUT1A EQB EQRMUTE1 IGND GND GND GND GND GND GND GND GND GND GND GND D11 D11 D9 D7 D6 D5 D4 D3 D2 D1 D8 D10 D9 DECK A/B D10 SPEED D9 B EQ A EQ AGC OFF D8 SPEED B EQ AGC GAIN 19.5dBRFCVCCVGGNDAGC TCAGC IN2REC IN2AGC OUT2REC OUT2D GNDXRESETDATADECK-APB-HEADBIasOSCRECPBGND RECPBGND 10k 12mH 820p 180p 150p GND 10k 12mH 820p 180p 150p GND R/P-HEADDECK-B12k 10k 2.2µ 0.018µ 47µ 100 GND GND GND 47µ 100 GND 0.018µ 10k 2.2µ GND 1k 0.1µ 0.1µ 100k 100k 27k 27k 0.47µ 0.1µ 4.7µ 10k 2.2µ 0.1µ 10k GND GND GND GND VDD or VCC 1k 2.7k 0.47µ 0.1µ 4.7µ 10k 2.2µ 100µ GND 100k GND GND VDD 2.2µ 2.2meg 47µ GND GND GND VCC GND GND GND GND GND GND GND GND 40 39 38 37 41 42 43 44 45 46 47 48 14 15 16 17 18 19 20 21 22 23 24 13 2 3 4 5 6 7 8 9 10 11 12 1 25 26 27 28 29 30 36 35 34 31 32 33 GND GND 2.7k 10µ 47µ VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 15 – CXA1898Q 1. System control mode Playback and recording equalizer (1) Playback equalizer (120µs/70µs) DECK-AB (serial data D10 (Pin 25)) A-EQ (Pin 10) B-EQ (Pin 11) L H L M/H L H 120µs (A DECK) 70µs (A DECK) According to A EQ control 120µs (B DECK) 70µs (B DECK) According to B EQ control (2) Recording equalizer (Normal, CrO2, Metal) B-EQ (Pin 11) REC MODE L Normal (Type I) M CrO2 (Type II) H Metal (Type IV) (3) Recording mute (Pin 12) Rec Mute Control voltage Mute OFF GND ≤ VCL ≤ 0.5V –7dB attenuation 2.0V Mute ON 3.5V ≤ VCH ≤ VCC Muting is achieved by varying the recording equalizer amplifier gain just like an electronic volume, according to the DC voltage applied to the REC MUTE pin. (4) FP CAL (Pin 4) The standard resistor setting is 27kΩ, but when resistance value is larger, fo (Hz) is low, and when resistance value is smaller, fo (Hz) is high. (5) Gp Cal (Pin 5) The standard resistor setting is 27kΩ, but when resistance value is larger, gain is larger, and when resistance value is smaller, gain is smaller. – 16 – CXA1898Q 2. 11-bit serial data interface • The DATA signal is taken in at the rising edge of the CLK signal. • The DATA signal is taken in to the internal shift register when the LATCH signal is low. (Outputs (Pins 13 to 22) hold the previous value while the LATCH signal is low.) • The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal. (Internal shift register data is loaded while the LATCH signal is high.) • The CLK signal of 11th bit should fall after the LATCH signal rises. • Reset is done when the XRESET pin is low. (asynchronous method) Outputs (Pins 13 to 22) are all high (open) during reset. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 M2 M1 PL2 PL1 BPB BPA PB-MUTE AGC-OFF SPEED DECK-AB REC-MUTE Pin 22 Pin 21 Pin 20 Pin 19 Pin 18 Pin 17 Pin 16 — Pin 15 — Pin 14/Pin 13 L L L L L L L AGC function stops Low, normal speed A DECK selected Low mute OFF H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) AGC function operates High (open) 1.7 B DECK selected High (open) mute ON Output pin Input set at low Input set at high Output DATA (Pin 25) Control signal D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 CLk (Pin 24) DATA (Pin 25) LATCH (Pin 23) XRESET (Pin 26) D11 – 17 – CXA1898Q • Make sure that RFC is 5.5V or more and XRESET is 1.5V or less, and 1µs or more when resetting by applying CR time constant to XRESET (Pin 26) and turning power ON. • When resetting with CPU or other when power is turned ON • Examples of AGC control during timer recording (1) Resets when power is turned ON (AGC function operates). (2) AGC is turned OFF after AGC inputs (Pins 6 and 31) rise. (External capacitor charge of AGC TC is discharged.) (3) AGC is turned ON and timer recording begins. 1µs or more 1.5V or less 5.5V or more RFC (Pin 36) XRESET (Pin 26) 1µs or more 5.0V 5.5V or more RFC (Pin 36) XRESET (Pin 26) 0V – 18 – CXA1898Q Circuit Diagram for 11-bit Serial Data Transfer Evaluation Tool D11H L D10H L D9H L D8H L D12H L D13H L D14H L D15H L 6 8 9 10 11 12 13 14 2 3 4 5 6 7 1 XQ2Q2XPR2CLK2D2XR2VDDVSSXQ1Q1XPR1CLK1D1XR174HC74 (1) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 XQ2Q2XPR2CLK2D2XR2VDDVSSXQ1Q1XPR1CLK1D1XR174HC74 (2) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 XQ2Q2XPR2CLK2D2XR2VDDVSSXQ1Q1XPR1CLK1D1XR174HC74 (3) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 XQ2Q2XPR2CLK2D2XR2VDDVSSXQ1Q1XPR1CLK1D1XR174HC74 (4) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 Y3A3B3Y4A4B4VDDVSSY2B2A2Y1B1A174HC00 8 9 10 11 12 13 14 2 3 4 5 6 7 1 Y3A3B3Y4A4B4VDDVSSY2B2A2Y1B1A174HC08 (2) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 Y3A3B3Y4A4B4VDDVSSY2B2A2Y1B1A174HC08 (1) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 Y4A4Y5A5Y6A6VDDVSSY3A3Y2A2Y1A174HC04 R5 10k ONOFFSTART3 ONOFFRESETC50.1µ4 C120.1µC90.1µC80.1µR3 10k R6 10k C40.1µ15 C140.1µC130.1µC200.1µ5 13 100R1612 1 14 8 9 10 11 12 13 14 2 3 4 5 6 7 1 Q1CLOCKRESETQ9Q8Q10Q11VDDVSSQ2Q3Q4Q7Q5Q6Q1274HC4040 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 XA2B2XRES2XQ2Q1C1R/C1VDDVSSR/C2C2Q2XQ1XRES1B1XA174HC123 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 B0A0B1A1A2B2A3VDDVSSA<BOUTA=BOUTA>BOUTA>BINA=BINA<BINB374HC85 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 XLOADENA 1RESETQ9Q8Q10Q11VDDVSSENA PDDDCDBDACLOCKXRESET74HC161 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 QHSERIALINABCDCLK2VDDVSSXQHHGFECLK1S/XL74HC165 (1) 15 16 C190.1µC180.1µ1248H L H L H L H L D4H L D5H L D6H L D7H L 8 9 10 11 12 13 14 2 3 4 5 6 7 1 QHSERIALINABCDCLK2VDDVSSXQHHGFECLK1S/XL74HC165 (2) 15 16 C170.1µC110.1µC100.1µD3H L D2H L D1H L 8 17 68k R17 11 C16 4.7µ C15 1000P R13 2.2k 1 R7220R8220R15220R14220R1110kR1210k9 16 R1 1M R2 220 C6 15P C7 15P 4.4MHz R4220R92202 LATCHCLKDATAXRESETDGND5VSW GNDGND 100µ/25V C21 15 16 19 100R18DGND EXCLK C30.1µC20.1µC0.1µEXCLK 250kHz500kHz100R19100R10 – 19 – CXA1898Q Timing Chart for 11-bit Serial Data Transfer Evaluation ToolDummyD1D2D3D4D5D6D7D8D9D10D112µsCOUNT RESETCLOCK STOP(14) RESET/CLOCK STOP and COUNT RESET(15) DATA HC165(16) CLOCK(17) = (8)(18)(19) LATCH(13)(12)(11) HC123(10) A = B, H(9)(8) CLK GATE CONT.(7) S/L(6) = (4)(5)(4)(3) START PULSE(2) CLK(1) CLK – 20 – CXA1898Q 3. AMS (1) AMS output logic AMS OUT (Pin 2) is an open collector output pin. When a 2.2kΩ resistor is connected to VDD: Low : approximately 0.5V (IOL = 2mA (max.)) High : VDD Fig. 1 shows the AMS block diagram. Fig. 1 AMS Block Diagram Fig. 2 shows the frequency response of the signal output from HPF. Fig. 2 Frequency Response Detection status AMS OUT (Pin 2) Signal detection L No signal detection H 2 3 1 48 PB OUT1 PB OUT2 20k20kSA LPF DET 25kHz 100k GND VDD VDD VDD GND AMS GND AMS OUT AMS FIL C1R1R2C2R3HPF AMS GAIN Inside IC fC G 10 1kHz 25kHz 100kHz GAIN (dB) f (Hz) – 21 – CXA1898Q (2) AMS level setting The AMS level is set by adjusting HPF gain and cut-off frequency with the external resistor and capacitor at Pin 48. G and fc in Fig. 2 are obtained from the following formula. G = 20log (1 + 100k/R) [dB] – (1) fc = 1/ (2 • π • C • R) [Hz] Full-wave rectifier is applied for the signal at DET. Signal detection time is set by the time constant of Pin 1 external resistor and capacitor. DET signal detection level: = –7.5dBm (typ.) = playback equalizer reference output level + AMS level + HPF gain – (2) Playback equalizer reference output level of –21dBm is 0dB. Ex.) To set AMS level at –25dB, determine and set the constant for Pin 48 external resistor. (Calculate assuming PBOUT1 = PBOUT2) First, get the required HPF gain from formula (2). –7.5dBm = –21dBm + (–25dB) + HPF gain, so HPF gain = 38.5dB. Next, get Pin 48 external resistance from formula (1). 38.5dB = 20log (1 + 100k/R), so R ≈ 1.2kΩ, and external resistance is 1.2kΩ. – 22 – CXA1898Q Quiescent current consumption vs. Supply voltage VCC-Supply voltage (V) 25 24 23 22 21 20 19 18 17 16 15 ICC-Quiescent current consumption (mA)6 7 8 9 10 11 Example of Representative Characteristics PB INPB FB1PB FB2PB OUTPlayback equalizer frequency response Frequency (Hz) 65 60 55 50 45 40 35 30 25 GAIN (dB)20 50 100 200 500 1k 2k 5k 10k 20k 50k 120µs – NS 120µs – HS 70µs – NS 70µs – HS M VCC = 8V 0.018µ 2.2k0.47µ47µ1002.2µ – 23 – CXA1898Q Recording equalizer frequency response Frequency (Hz) 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 –2 Output response (dB)20 50 100 200 500 1k 2k 5k 10k 20k 50k VCC = 8V 0dB = NORM – NS, 315Hz, –30dBm (Tape) (Speed) NORM– CrO2– METAL– NS NS NS 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 –2 20 50 100 200 500 1k 2k 5k 10k 20k 50k VCC = 8V 0dB = NORM – NS, 315Hz, –30dBm (Tape) (Speed) NORM– CrO2– METAL– HS HS HS Recording equalizer frequency response Frequency (Hz) Output response (dB) – 24 – CXA1898Q RMUTE1 (Pin 1) voltage 0.0 1.0 2.0 3.0 4.0 5.0 6.0 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 Output level vs. Mute voltage VCC = 8V (Tape) (Speed) NORM– NS 0dB = reference output level +8dB f = 1kHz Output level (dB)AMS no signal detection level frequency response Frequency (Hz) 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 AMS input level (playback equalizer output level) (dB)20 50 100 200 500 1k 2k 5k 10k 20k 50k VCC = 8V 120µs – NS AMS OUT 5V 0dB = –21dBm, 315Hz (playback equalizer reference output level) A B A : Pin 48 for R9.1k, C0.015µ B : Pin 48 for R1k, C0.1µ AMS GAINAMS FILAMS OUT0.1µ100k100kto5V 2 48 1 A : 0.015µ 9.1k B : 0.1µ 1k – 25 – CXA1898Q AGC Output response 10 5 0 –5 –10 –15 Output level (dBm)–35 –30 –25 –20 –15 –10 –5 Input level (dBm) AGC OFF AGC ON VCC = 8V 1kHz 32 47µ 300k AGC TCRecording equalizer total harmonic distortion –15 –10 –5 0 5 10 Output level (dB) T.H.D. + Noise (%)2.0 1.0 0.5 0.2 0.1 VCC = 8V Norm – NS mode RL = 2.7kΩ 1kHz 0dB = –10dBm Playback equalizer total harmonic distortion –30 –25 –20 –15 –10 –5 Output level (dB) T.H.D. + Noise (%)2.0 1.0 0.5 0.2 0.1 VCC = 8V 120µs – NS mode RL = 2.7kΩ 1kHz – 26 – CXA1898Q Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE M PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 48PIN QFP (PLASTIC) 15.3 ± 0.4 12.0 – 0.1 + 0.4 0.8 0.3 – 0.1 + 0.15 ± 0.12 13 24 25 36 37 48 1 12 2.2 – 0.15 + 0.35 0.9 ± 0.20.1 – 0.1 + 0.2 13.50.15 0.15 – 0.05 + 0.1 QFP-48P-L04 ∗QFP048-P-1212-B 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
