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Description The CXD2545Q is a digital signal processor IC with a built-in digital servo for CD players. This IC is broadly divided into a digital signal processor block and a digital servo block, and these blocks possess the following functions. Digital Signal Processor Block • Wide frame jitter margin (±28 frames) due to a built-in 32K RAM • The bit clock, which strobes the EFM signal, is generated by the digital PLL. • Enhanced EFM frame sync signal protection • Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction • Quadruple-speed, double-speed and variable pitch playback • Noise reduction during track jumps • Auto zero-cross mute • Subcode demodulation and Sub Q data error detection • Digital spindle servo (with oversampling filter) • Asymmetry compensation circuit • Error correction monitor signal, etc. output from a new CPU interface • Servo auto sequencer • Fine search performs track jumps with high accuracy • Digital level meter, peak meter • Bilingual compatible Digital Servo Block • Microcomputer software-based flexible servo control • Servo error signal, offset cancel function • Servo loop, auto gain control function • E:F balance, focus bias adjustment function Features • All digital signals produced during playback processed with a single chip • Allows highly integrated chip mounting by incorporating the RAM and digital servo on-chip Absolute Maximum Ratings • Supply voltage VDD –0.3 to 7.0 V • Input voltage VI –0.3 to +7.0 V (VSS –0.3V to VDD +0.3V) • Output voltage VO –0.3 to +7.0 V • Storage temperature Tstg –40 to +125 °C • Supply voltage difference VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V Recommended Operating Conditions • Supply voltage VDD∗ 4.50 to 5.50 V • Operating temperature Topr –20 to +75 °C ∗ The VDD (min.) for the CXD2545Q varies according to the playback speed and built-in VCO selection. The VDD (min.) is 4.50V when high-speed VCO and quadruple-speed playback are selected (variable pitch off). The VDD (min.) for the CXD2545Q under various conditions are as shown in the following table. Dashes indicate that there is no assurance of the processor operating. All values are for variable pitch off. ∗ 1 When the internal operation of the LSI is set to normal-speed playback and the operating clock of the signal processor is doubled, double-speed playback results. ∗ 2 When the internal operation of the LSI is set to double-speed mode and the crystal oscillating frequency is halved in low power consumption mode, normal-speed playback results. I/O Capacitance • Input capacitance CI 12 (max.) pF • Output capacitance CO 12 (max.) pF When at high impedance Note) Measurement conditions VDD = VI = 0V fM = 1MHz – 1 – CXD2545Q E95134A6X-PS CD Digital Signal Processor with Built-in Digital Servo Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. Playback speed × 4 × 2∗ 1 × 2 × 1 × 1∗ 2 4.50 4.00 3.40 3.40 3.40 — — 4.00 3.40 3.40 VCO high speed VCO normal speed VDD (min.) [V] 100 pin QFP (Plastic) – 2 – CXD2545Q Block Diagram FSTOFSOF CLOCK GENERATOR MUX 32K RAM ERROR CORRECTOR CPU INTERFACE DIGITAL OUT PEAK DETECTOR ADDRESS GENERATOR PRIORITY ENCODER D/A DATA PROCESSOR TIMING GENERATOR 2 SERVO AUTO SEQUENCER CLV PROCESSOR 18-TIMES OVERSAMPLING FILTER NOISE SHAPER DIGITAL PLL VARI-PITCH DOUBLE SPEED EFM DEMODULATOR SYNC PROTECTOR TIMING GENERATOR 1 SUBCODE P to W PROCESSOR SUBCODE Q PROCESSOR REGISTERSERIAL/PARALLELPROCESSOR14 16 17 19 20 21 23 40 35 43 70 67 63 64 62 71 81 88 87 86 79 80 15 41 65 90 12 13 18 39 38 36 34 31 32 33 42 69 68 72 73 74 75 76 77 78 97 96 95 94 91 92 93 SERVO INTERFACE MIRR SERVO DSP FOCUS SERVO TRACKING SERVO SLED SERVO PWM GENERATOR FOCUS PWM GENERATOR TRACKING PWM GENERATOR SLED PWM GENERATOR SFDR, SFON 2 SRDR, SRON 2 TFDR, TFON 2 TRDR, TRON 2 FFDR, FFON 2 FRDR, FRON 2 A/D CONVERTER 26 27 28 29 30 16 FOK DFCT MIRR SENS XLAT CLOK DATA MD2 DOUT MUTE DA01 to 16 PSSL XTAIXTAOXTSLVCKIVPCOC16M PDO VCOI VCOO PCO FILI FILO CLTV RFAC ASYI ASYO ASYE WFCK SCOR EXCK SBSO EMPH SQCK SQSO MON FSW MDP MDS RFDC TE SE FE VC TESTTES2TES3AVDDAVDDAVSSAVSSVDDVDDVSSVSSXRSTDFCT FOK SWITCH & BUFFER 24 25 RFCADIOCOUT 89 Signal Processor Block Servo Block ASYMMETRY CORRECTION – 3 – CXD2545Q Pin Configuration 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 51 52 53 54 55 56 57 58 59 60 63 64 61 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 24 25 26 27 28 29 30 81 82 83 84 88 87 86 85 89 90 100 99 98 97 96 95 94 91 92 93 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 SRONSRDRSFONTFDRTRONTRDRTFONFFDRFRONFRDRFFONVCOOVCOITESTVSSTES2TES3PDOVPCOVCKIAVDDIGENAVSSADIORFCRFDCTESEFEVCSENSMUTESQCKSQSOEXCKSBSOSCORWFCKEMPHDOUTMD2C16MFSOFFSTOFSTIVSSXTSLXTAOXTAIDA01DA02DA03DA04DA05DA06DA07DA08DA09DA10DA11SFDR SSTP LOCK MDS MDP MON FSW FOK DFCT MIRR VDD COUT CLOK XLAT DATA ATSK DFSW SCLK DIRC XRST FILO FILI PCO CLTV AVSS RFAC BIAS ASYI ASYO AVDD VDD ASYE PSSL WDCK LRCK DA16 DA15 DA14 DA13 DA12 Pin Description Pin No. Symbol I/O Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SRON SRDR SFON TFDR TRON TRDR TFON FFDR FRON FRDR FFON VCOO VCOI TEST VSS O O O O O O O O O O O O I I — Sled drive output. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Focus drive output. Focus drive output. Analog EFM PLL oscillation circuit output. Analog EFM PLL oscillation circuit input. fLOCK = 8.6436MHz. Test pin. Normally GND. Digital GND. – 4 – CXD2545Q Pin No. Symbol I/O Description 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TES2 TES3 PDO VPCO VCKI AVDD IGEN AVSS ADIO RFC RFDC TE SE FE VC FILO FILI PCO CLTV AVSS RFAC BIAS ASYI ASYO AVDD VDD ASYE PSSL WDCK LRCK DA16 DA15 DA14 DA13 DA12 DA11 DA10 I I O O I — I — O I I I I I I O I O I — I I I O — — I I O O O O O O O O O Test pin. Normally GND. Test pin. Normally GND. Analog EFM PLL charge pump output. Variable pitch PLL charge pump output. Variable pitch clock input from the external VCO. fcenter = 16.9344MHz. Analog power supply. Reference resistance connection for digital servo operational amplifier current source. Analog GND. A/D converter input monitor. RFDC input low-pass filter capacitor connection. RF signal input. Input range: 2.15 to 5.0V (when VDD = AVDD = 5.0V). Tracking error signal input. Input range: 2.5 ±1.0V (when VDD = AVDD = 5.0V). Sled error signal input. Input range: 2.5 ±1.0V (when VDD = AVDD = 5.0V). Focus error signal input. Input range: 2.5 ±1.0V (when VDD = AVDD = 5.0V). Center voltage input. Master PLL filter output. Master PLL filter input. Master PLL charge pump output. Master PLL VCO control voltage input. Analog GND. EFM signal input. Constant current input of asymmetry circuit. Comparator voltage input of asymmetry circuit. EFM full-swing output (low = VSS, high = VDD). Analog power supply. Digital power supply. Asymmetry circuit on/off (low = off, high = on). Audio data output mode switching input. Low: serial output; high: parallel output. D/A interface and word clock for 48-bit slot. f = 2Fs. D/A interface and LR clock for 48-bit slot. f = Fs. DA16 output when PSSL = 1. 48-bit slot serial data when PSSL = 0. DA15 output when PSSL = 1. 48-bit slot bit clock when PSSL = 0. DA14 output when PSSL = 1. 64-bit slot serial data when PSSL = 0. DA13 output when PSSL = 1. 64-bit slot bit clock when PSSL = 0. DA12 output when PSSL = 1. 64-bit slot LR clock when PSSL = 0. DA11 output when PSSL = 1. GTOP output when PSSL = 0. DA10 output when PSSL = 1. XUGF output when PSSL = 0. – 5 – CXD2545Q 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 DA09 DA08 DA07 DA06 DA05 DA04 DA03 DA02 DA01 XTAI XTAO XTSL VSS FSTI FSTO FSOF C16M MD2 DOUT EMPH WFCK SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DIRC SCLK DFSW ATSK O O O O O O O O O I O I — I O O O I O O O O O I O I I O I I I I I DA09 output when PSSL = 1. XPLCK output when PSSL = 0. DA08 output when PSSL = 1. GFS output when PSSL = 0. DA07 output when PSSL = 1. RFCK output when PSSL = 0. DA06 output when PSSL = 1. C2PO output when PSSL = 0. DA05 output when PSSL = 1. XRAOF output when PSSL = 0. DA04 output when PSSL = 1. MNT3 output when PSSL = 0. DA03 output when PSSL = 1. MNT2 output when PSSL = 0. DA02 output when PSSL = 1. MNT1 output when PSSL = 0. DA01 output when PSSL = 1. MNT0 output when PSSL = 0. Crystal oscillation circuit input. Input 16.9344MHz or 33.8688MHz. Crystal oscillation circuit output. Crystal selector input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz (during normal-speed playback). Digital GND. Digital servo block reference clock input. 2/3 frequency divider output for Pins 62 and 63. This pin does not change with variable pitch. 1/4 frequency divider output for Pins 62 and 63. This pin does not change with variable pitch. 16.9344MHz output. This pin changes simultaneously with the variable pitch (during normal-speed playback). Digital Out on/off control (low = off, high = on). Digital Out output. Playback disc emphasis mode output. (Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis.) WFCK output. Subcode sync output. (Outputs a high signal when either subcode sync S0 or S1 is detected.) Sub P to W serial output. SBSO readout clock input. Sub Q 80-bit output. PCM peak and level data 16-bit output. SQSO readout clock input. Mute switching pin (high: mute). SENS output to CPU. System reset (reset when low). Used for 1 track jumps. (Input VDD level when not used.) SENS serial data readout clock. DFCT switching pin (high: DFCT countermeasure circuit off). Anti-shock pin. Pin No. Symbol I/O Description – 6 – CXD2545Q Notes) • The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's complement output. • GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) • XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection. • XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. • The GFS signal goes high when the frame sync and the insertion protection timing match. • RFCK is derived from the crystal accuracy, and has a cycle of 136µs. • C2PO represents the data error status. • XRAOF is generated when the 32K RAM exceeds the ±28 F jitter margin. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DATA XLAT CLOK COUT VDD MIRR DFCT FOK FSW MON MDP MDS LOCK SSTP SFDR I I I O — O O O O O O O O I O Serial data input from CPU. Latch input from CPU. Serial data transfer clock input from CPU. Track count signal input. Digital power supply. Mirror signal output. Defect signal output. Focus OK output. Spindle motor output filter switching output. Spindle motor on/off control output. Spindle motor servo control. Spindle motor servo control. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Disc innermost track detective signal pin. Sled drive output. Pin No. Symbol I/O Description – 7 – CXD2545Q Electrical Characteristics 1. DC Characteristics (VDD = AVDD = 5.0V ±10%, Vss = AVss = 0V, Topr = –20 to +75°C) Item Input voltage (1) Input voltage (2) Input voltage (3) Output voltage (1) Output voltage (2) Output voltage (3) Output voltage (4) Input leak current (1) Input leak current (2) Input leak current (3) Tri-state pin output leak current ∗ 1 ∗ 2 ∗ 3, 11 ∗ 4 ∗ 5 ∗ 6 ∗ 7 ∗ 1, 2, 3 ∗ 8 ∗ 9 ∗ 10 Schmitt input Analog input IOH = –4mA IOL = 4mA IOH = –2mA IOL = 4mA IOL = 4mA IOH = –0.28mA IOL = 0.36mA VI = 0 to 5.5V VI = 1.5 to 3.5V VI = 0 to 5.0V VO = 0 to 5.5V High level input voltage Low level input voltage High level input voltage Low level input voltage Input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Low level output voltage High level output voltage Low level output voltage VIH (1) VIL (1) VIH (2) VIL (2) VIN(3) VOH(1) VOL(1) VOH(2) VOL(2) VOL(3) VOH(4) VOL(4) ILI (1) ILI (2) ILI (3) ILO 0.7VDD 0.8VDD Vss VDD – 0.8 0 VDD – 0.8 0 0 VDD – 0.5 0 –10 –20 –40 –5 0.3VDD 0.2VDD VDD VDD 0.4 VDD 0.4 0.4 VDD 0.4 10 20 600 5 V V V V V V V V V V V V µA µA µA µA Conditions Min. Typ. Max. Unit Applicable pins Applicable pins ∗ 1 XTSL, DATA, XLAT, MD2, PSSL, TEST, TES2, TES3, DFSW, DIRC, SSTP, ATSK ∗ 2 CLOK, XRST, EXCK, SQCK, MUTE, VCKI, ASYE, FSTI, SCLK ∗ 3 CLTV, FILI, RFAC, ASYI, RFDC, TE, SE, FE, VC ∗ 4 MDP, PDO, PCO, VPCO ∗ 5 ASYO, DOUT, FSTO, FSOF, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, SENS, MDS, DA01 to DA16, LRCK, WFCK, FOK, COUT, MIRR, DFCT, FFON, FRDR, FRON, FFDR, TFON, TRDR, TRON, TFDR, SFON, SRDR, SRON, SFDR ∗ 6 FSW ∗ 7 FILO ∗ 8 TE, SE, FE, VC ∗ 9 RFDC ∗ 10 SENS, MDS, MDP, FSW, PDO, PCO, VPCO ∗ 11 RFC – 8 – CXD2545Q 2. AC Characteristics (1) XTAI pin, VCOI pin (a) When using self-excited oscillation (Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%) (b) When inputting pulses to XTAI and VCOI (Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%) (c) When inputting sine waves to the XTAI and VCOI pins via a capacitor (Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%) Oscillation frequency fMAX 7 34 MHz Item Symbol Min. Typ. Max. Unit High level pulse width tWHX 13 500 ns Low level pulse width tWLX 13 500 ns Pulse cycle tCX 26 1000 ns Input high level VIHX VDD – 1.0 V Input low level VILX 0.8 V Rise time, fall time tR, tF 10 ns Item Symbol Min. Typ. Max. Unit Input amplitude VI 2.0 VDD + 0.3 Vp-p Item Symbol Min. Typ. Max. Unit tR tF tWHX tWLX tCX VILX VIHX × 0.1 VIHX × 0.9 VIHX XTAI VDD/2 – 9 – CXD2545Q (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = AVDD = 5.0V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C) Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width fCK tWCK tSU tH tD tWL fT tWT 750 300 300 300 750 750 0.65 0.65 MHz ns ns ns ns ns MHz ns Item Symbol Min. Typ. Max. Unit tWCK tWCK 1/fCK tH tSU tWL tD 1/fT tWT tWT tH tSU CLOK DATA XLAT EXCK SQCK SBSO SQSO – 10 – CXD2545Q (4) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 5.0V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C) COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency fCOUT fMIRR fDFCTH 40 40 5 kHz kHz kHz ∗ 1 ∗ 2 ∗ 3 Item Symbol Min. Typ. Max. Unit Conditions ∗ 1 When using a high-speed traverse TZC. ∗ 2 When the RF signal continuously satisfies the following conditions during the above traverse. • A = 0.6 to 1.3V • = less than 25% ∗ 3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. (3) SCLK pin SCLK frequency SCLK pulse width Delay time fSCLK tSPW tDLS 500 15 1 MHz ns µs Item Symbol Min. Typ. Max. Unit tSPW tDLS 1/fSCLK MSB LSB ••• ••• XLAT SCLK Serial Read Out Data (SENS) A B B A + B – 11 – CXD2545Q Contents  CPU Interface §1-1. CPU Interface Timing .......................................................................................................................12 §1-2. CPU Interface Command Table........................................................................................................12 §1-3. CPU Command Presets ...................................................................................................................22 §1-4. Description of SENS Signals ............................................................................................................27  Description of CD Signal Processing-System Commands and Functions §2-1. Description of Commands and Data Sets.........................................................................................29 §2-2. Subcode Interface.............................................................................................................................43 §2-3. Digital PLL ........................................................................................................................................48 §2-4. EFM Frame Sync Protection.............................................................................................................50 §2-5. Error Correction ................................................................................................................................50 §2-6. DA Interface......................................................................................................................................51 §2-7. Digital Out .........................................................................................................................................54 §2-8. Servo Auto Sequencer......................................................................................................................54 §2-9. Digital CLV........................................................................................................................................63 §2-10. Asymmetry Compensation................................................................................................................64 §2-11. Playback Speed................................................................................................................................64  Description of Servo Signal Processing-System Functions and Commands §3-0. General Description of the Servo Signal Processing System...........................................................65 §3-1. Servo Master Clock (MCK) ...............................................................................................................66 §3-2. AVRG Measurement and Compensation .........................................................................................66 §3-3. E:F Balance Adjustment Function ....................................................................................................68 §3-4. FCS Bias Adjustment Function.........................................................................................................68 §3-5. AGCNTL Function ............................................................................................................................70 §3-6. FCS Servo and FCS Search.............................................................................................................72 §3-7. TRK and SLD Servo Control.............................................................................................................73 §3-8. MIRR and DFCT Signal Generation .................................................................................................74 §3-9. DFCT Countermeasure Circuit .........................................................................................................75 §3-10. Anti-Shock Circuit .............................................................................................................................75 §3-11. Brake Circuit .....................................................................................................................................76 §3-12. COUT Signal.....................................................................................................................................77 §3-13. Serial Readout Circuit .......................................................................................................................77 §3-14. Writing the Coefficient RAM..............................................................................................................78 §3-15. PWM Output .....................................................................................................................................78 §3-16. DIRC Input Pin..................................................................................................................................80 §3-17. Servo Status Changes Produced by the LOCK Signal.....................................................................81 §3-18. Description of Commands and Data Sets.........................................................................................82 §3-19. List of Servo Filter Coefficients .........................................................................................................91 §3-20. FILTER Composition ........................................................................................................................93 §3-21. TRACKING and FOCUS Frequency Response .............................................................................100  Application Circuit §4-1. Application Circuit ...........................................................................................................................101 Explanation of abbreviations AVRG: Average AGCNTL: Automatic gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect – 12 – CXD2545Q  CPU Interface §1-1. CPU Interface Timing • CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 750ns or more D18 D19 D20 D21 D22 D23 750ns or more Valid CLOK DATA XLAT Registers • The internal registers are initialized by a reset when XRST = 0. §1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 4 to 6 7 8 to A B C to E 8bit 8 to 24bit 16bit 20bit 16bit 20bit 16bit Total bit length – 13 – CXD2545Q FOCUS SERVO ON(FOCUS GAIN NORMAL)FOCUS SERVO ON(FOCUS GAIN DOWN)FOCUS SERVO OFF,0V OUTFOCUS SERVO OFF,FOCUS SEARCH VOLTAGE OUTFOCUS SEARCH VOLTAGE DOWNFOCUS SEACH VOLTAGE UPANTI SHOCK ONANTI SHOCK OFFBRAKE ONBRAKE OFFTRACKING GAIN NORMALTRACKING GAIN UPTRACKING GAIN UP FILTER SELECT 1TRACKING GAIN UP FILTER SELECT 211000010——————01————0—10——————0111————01——————01——————10————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————010 0 0 00 0 0 1FOCUSCONTROLTRACKINGCONTROLRegisterCommandAddressD23 to D20Data 1D19D18D17D16Data 2D15D14D13D12Data 3D11D10D9D8Data 4D7D6D5D4Data 5D3D2D1D0Command Table ($0X to 1X)—: Don’t care – 14 – CXD2545Q TRACKING SERVO OFFTRACKING SERVO ONFORWARD TRACK JUMPREVERSE TRACK JUMPSLED SERVO OFFSLED SERVO ONFORWARD SLED MOVEREVERSE SLED MOVESLED KICK LEVEL(±1 + basic value) (Default)SLED KICK LEVEL(±2 + basic value)SLED KICK LEVEL(±3 + basic value)SLED KICK LEVEL(±4 + basic value)0011————0000000000110101————————————————————————————————————————————————————————————————0101————————0011————0101————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————230 0 1 00 0 1 1TRACKINGMODESELECTRegisterCommandAddressD23 to D20RegisterCommandAddressD23 to D20Data 1D19D18D17D16Data 1D19D18D17D16Data 2D15D14D13D12Data 2D15D14D13D12Data 3D11D10D9D8Data 4D7D6D5D4Data 5D3D2D1D0Data 3D11D10D9D8Data 4D7D6D5D4Data 5D3D2D1D0—: Don’t careCommand Table ($2X to 3X) – 15 – CXD2545Q KRAM DATA (K00)SLED INPUT GAINKRAM DATA (K01)SLED LOW BOOST FILTER A-HKRAM DATA (K02)SLED LOW BOOST FILTER A-LKRAM DATA (K03)SLED LOW BOOST FILTER B-HKRAM DATA (K04)SLED LOW BOOST FILTER B-LKRAM DATA (K05)SLED OUTPUT GAINKRAM DATA (K06)FOCUS INPUT GAINKRAM DATA (K07)SLED AUTO GAINKRAM DATA (K08)FOCUS HIGH CUT FILTER AKRAM DATA (K09)FOCUS HIGH CUT FILTER BKRAM DATA (K0A)FOCUS LOW BOOST FILTER A-HKRAM DATA (K0B)FOCUS LOW BOOST FILTER A-LKRAM DATA (K0C)FOCUS LOW BOOST FILTER B-HKRAM DATA (K0D)FOCUS LOW BOOST FILTER B-LKRAM DATA (K0E)FOCUS PHASE COMPENSATE FILTER AKRAM DATA (K0F)FOCUS DEFECT HOLD GAIN0000000011111111000011110000111100110011001100110101010101010101KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD030 0 1 10 1 0 00 0 0 0SELECTRegisterCommandAddress 1D23 to D20Address 2D19 to D16Address 3D15 to D12Address 4D11D10D9D8Data 1D7D6D5D4Data 2D3D2D1D0Command Table ($340X) – 16 – CXD2545Q KRAM DATA (K10)FOCUS PHASE COMPENSATE FILTER BKRAM DATA (K11)FOCUS OUTPUT GAINKRAM DATA (K12)ANTI SHOCK INPUT GAINKRAM DATA (K13)FOCUS AUTO GAINKRAM DATA (K14)HPTZC / AUTO GAIN HIGH PASS FILTER AKRAM DATA (K15)HPTZC / AUTO GAIN HIGH PASS FILTER BKRAM DATA (K16)ANTI SHOCK HIGH PASS FILTER AKRAM DATA (K17)HPTZC / AUTO GAIN LOW PASS FILTER BKRAM DATA (K18)FIXKRAM DATA (K19)TRACKING INPUT GAINKRAM DATA (K1A)TRACKING HIGH CUT FILTER AKRAM DATA (K1B)TRACKING HIGH CUT FILTER BKRAM DATA (K1C)TRACKING LOW BOOST FILTER A-HKRAM DATA (K1D)TRACKING LOW BOOST FILTER A-LKRAM DATA (K1E)TRACKING LOW BOOST FILTER B-HKRAM DATA (K1F)TRACKING LOW BOOST FILTER B-L0000000011111111000011110000111100110011001100110101010101010101KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD030 0 1 10 1 0 00 0 0 1SELECTRegisterCommandAddress 1D23 to D20Address 2D19 to D16Address 3D15 to D12Address 4D11D10D9D8Data 1D7D6D5D4Data 2D3D2D1D0Command Table ($341X) – 17 – CXD2545Q KRAM DATA (K20)TRACKING PHASE COMPENSATE FILTER AKRAM DATA (K21)TRACKING PHASE COMPENSATE FILTER BKRAM DATA (K22)TRACKING OUTPUT GAINKRAM DATA (K23)TRACKING AUTO GAINKRAM DATA (K24)FOCUS GAIN DOWN HIGH CUT FILTER AKRAM DATA (K25)FOCUS GAIN DOWN HIGH CUT FILTER BKRAM DATA (K26)FOCUS GAIN DOWN LOW BOOST FILTER A-HKRAM DATA (K27)FOCUS GAIN DOWN LOW BOOST FILTER A-LKRAM DATA (K28)FOCUS GAIN DOWN LOW BOOST FILTER B-HKRAM DATA (K29)FOCUS GAIN DOWN LOW BOOST FILTER B-LKRAM DATA (K2A)FOCUS GAIN DOWN PHASE COMPENSATE FILTER AKRAM DATA (K2B)FOCUS GAIN DOWN DEFECT HOLD GAINKRAM DATA (K2C)FOCUS GAIN DOWN PHASE COMPENSATE FILTER BKRAM DATA (K2D)FOCUS GAIN DOWN OUTPUT GAINKRAM DATA (K2E)NOT USEDKRAM DATA (K2F)NOT USED0000000011111111000011110000111100110011001100110101010101010101KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD030 0 1 10 1 0 00 0 1 0SELECTRegisterCommandAddress 1D23 to D20Address 2D19 to D16Address 3D15 to D12Address 4D11D10D9D8Data 1D7D6D5D4Data 2D3D2D1D0Command Table ($342X) – 18 – CXD2545Q KRAM DATA (K30)FIXKRAM DATA (K31)ANTI SHOCK LOW PASS FILTER BKRAM DATA (K32)NOT USEDKRAM DATA (K33)ANTI SHOCK HIGH PASS FILTER B-HKRAM DATA (K34)ANTI SHOCK HIGH PASS FILTER B-LKRAM DATA (K35)ANTI SHOCK FILTER COMPARATE GAINKRAM DATA (K36)TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37)TRACKING GAIN UP2 HIGH CUT FILTER BKRAM DATA (K38)TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39)TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A)TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B)TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C)TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D)TRACKING GAIN UP PHASE COMPENSATE FILTER BKRAM DATA (K3E)TRACKING GAIN UP OUTPUT GAINKRAM DATA (K3F)NOT USED0000000011111111000011110000111100110011001100110101010101010101KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD030 0 1 10 1 0 00 0 1 1SELECTRegiaterCommandAddress 1D23 to D20Address 2D19 to D16Address 3D15 to D12Address 4D11D10D9D8Data 1D7D6D5D4Data 2D3D2D1D0Command Table ($343X) – 19 – CXD2545Q KRAM DATA (K40)TRACKING HOLD FILTER INPUT GAINKRAM DATA (K41)TRACKING HOLD FILTER A-HKRAM DATA (K42)TRACKING HOLD FILTER A-LKRAM DATA (K43)TRACKING HOLD FILTER B-HKRAM DATA (K44)TRACKING HOLD FILTER B-LKRAM DATA (K45)TRACKING HOLD FILTER OUTPUT GAINKRAM DATA (K46)NOT USEDKRAM DATA (K47)NOT USEDKRAM DATA (K48)FOCUS HOLD FILTER INPUT GAINKRAM DATA (K49)FOCUS HOLD FILTER A-HKRAM DATA (K4A)FOCUS HOLD FILTER A-LKRAM DATA (K4B)FOCUS HOLD FILTER B-HKRAM DATA (K4C)FOCUS HOLD FILTER B-LKRAM DATA (K4D)FOCUS HOLD FILTER OUTPUT GAINKRAM DATA (K4E)NOT USEDKRAM DATA (K4F)NOT USED0000000011111111000011110000111100110011001100110101010101010101KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD7KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD6KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD5KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD4KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD3KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD2KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD1KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD0KD030 0 1 10 1 0 00 1 0 0SELECTRegisterCommandAddress 1D23 to D20Address 2D19 to D16Address 3D15 to D12Address 4D11D10D9D8Data 1D7D6D5D4Data 2D3D2D1D0Command Table ($344X) – 20 – CXD2545Q 0 0 1 111100000110011FOCUS BIAS DATATRVSC DATAFOCUS SEARCH SPEED/VOLTAGE/AUTO GAINDTZC/TRACK JUMPVOLTAGE/AUTO GAINFZSL/SLED MOVE/Voltage/AUTO GAINLEVEL/AUTO GAIN/DFSW/ (Initialize)SERIAL DATA READ MODE/SELECTFOCUS BIASOperation for MIRR/DFCT/FOKTZC for COUT SLCT HPTZC (Default)TZC for COUT SLCT DTZCFilterOthers30 0 1 10 0 1 100110000111111110010FB9TV9FB8TV8FB7TV7FB6TV6FB5TV5FB4TV4FB3TV3FB2TV2FB1TV1—TV000011111010101FT10FZSHVCLMDAC0SFO2FT0DTZCFZSLVCLCSD6FBONSFO1FS5TJ5SM5FLMSD50SDF2FS4TJ4SM4FLC0SD40SDF1FS3TJ3SM3RFLMSD30MAX2FS2TJ2SM2RFLCSD20MAX1FS1TJ1SM1AGFSD10SFOXFS0TJ0SM0AGTSD00BTFFTZ0AGSDFSW00D2V2FG6TG6AGJLKSW00D2V1FG5TG5AGGFTBLM00D1V2FG4TG4AGGTTCLM00D1V1FG3TG3AGV1FLC1000FG2TG2AGV2TLC2000FG1TG1AGHSTLC1000FG0TG0AGHTTLC00000 0 1 11111111101F1NM0F1DM0F3NMXT4DF3DMXT2DT1NM0T1UMDRR2T3NMDRR1T3UMDRR0DFIS0TLCDASFGRFLP00LPAS0SRO10SRO00000110001————————————————————————————————0 0 1 1SELECTRegisterCommandAddress 1D23 to D20D19D18D17D16Address 2D15D14D13D12Data 1D11D10D9D8Data 2D7D6D5D4Data 3D3D2D1D0AddressD23 to D20D19D18D17D16Data 1D15D14D13D12Data 2D11D10D9D8Data 3D7D6D5D4Data 4D3D2D1D0AddressD23 to D20D19D18D17D16Data 1D15D14D13D12Data 2D11D10D9D8Data 3D7D6D5D4Data 4D3D2D1D0AddressD23 to D20D19D18D17D16Data 1D15D14D13D12Data 2D11D10D9D8Data 3D7D6D5D4Data 4D3D2D1D0Command Table ($34FX to 3FX)—: Don’t care – 21 – CXD2545Q Auto sequenceBlind (A, E),Brake (B),Overflow (C, D)Sled kick, brake (D), Kick (F)Auto sequence (N) track jump count settingMODE settingFunction specificationAudio CTRLTraverse monitor counter settingSpindle servo coefficient settingCLV CTRLCLV MODE0 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 0AS3TR3SD332,768CD-ROMDCLVON-OFFVariUp32,768GainMDP1DCLVPWM MDCM3AS2TR2SD216,384DOUTMuteDSPBON-OFFVariDown16,384GainMDP0TBCM2AS1TR1SD18,192D. outMute-FASEQON-OFFMute8,192GainMDS1TPCM1AS0TR0SD04,096WSELDPLLON-OFFATT4,096GainMDS0GainCLVSCM0MT30KF32,048VCO SELBiliGLMAINPTC12,048000MT20KF21,024ASHSBiliGLSUBPTC21,024GainDCLV000MT10KF1512SOCTFLFC0512000MT00KF0256000256000LSSL00128000128000000640006400000032000320000001600016000———8———8——————4———4——————2———2——————1———1———————————————————————————————————————————————456789ABCDERegisterCommandAddressD23 to D20Data 1D19D18D17D16Data 2D15D14D13D12Data 3D11D10D9D8Data 4D7D6D5D4Data 5D3D2D1D0Command Table ($4X to EX)—: Don’t care – 22 – CXD2545Q FOCUS SERVO OFF,0V OUTTRACKING GAIN UP FILTER SELECT 1TRACKING SERVO OFFSLED SERVO OFFSLED KICK LEVEL(±1 + basic value) (Default)KRAM DATA($3400XX to $344fXX)000000000010————————————————————————————————————————————————0120 0 0 00 0 0 10 0 1 0FOCUS CONTROLTRACKINGCONTROLTRACKINGMODERegisterCommandAddressD23 to D20Data 1D19D18D17D16Data 2D15D14D13D12Data 3D11D10D9D8Data 4D7D6D5D4Data 5D3D2D1D0RegisterCommand3SELECTAddressD23 to D200 0 1 10 0 1 101000See the coefficient preset values table.0000————————————————Data 1D19D18D17D16Data 2D15D14D13D12Data 3D11D10D9D8Data 4D7D6D5D4Data 5D3D2D0D0Address 1D23 to D20D19D18D17D16Address 2D15D14D13D12Address 3D11D10D9D8Data 1D7D6D5D4Data 2D3D2D0D0§1-3. CPU Command PresetsCommand Preset Table ($0X to 34X)—: Don’t care – 23 – CXD2545Q 0 0 1 111100000110011FOCUS BIAS DATATRVSC DATAFOCUS SEARCH SPEED/VOLTAGE/AUTO GAINDTZC/TRACK JUMPVOLTAGE/AUTO GAINFZSL/SLED MOVE/Voltage/AUTO GAINLEVEL/AUTO GAIN/DFSW/ (Initialize)SERIAL DATA READ MODE/SELECTFOCUS BIASOperation for MIRR/DFCT/FOKTZC for COUT SLCT HPTZC FilterOthers30 0 1 10 0 1 100110000111111110010000000000000000000—00001111101010100000011010001000000110100001100000010000001000000000000001000000000011110000001000111100001100000011000010000000 0 1 111111110100000000000000000000000000000000100————————————————0 0 0 1SELECTRegisterCommandAddress 1D23 to D20D19D18D17D16Address 2D15D14D13D12Data 1D11D10D9D8Data 2D7D6D5D4Data 3D3D2D1D0AddressD23 to D20D19D18D17D16Data 1D15D14D13D12Data 2D11D10D9D8Data 3D7D6D5D4Data 4D3D2D1D0AddressD23 to D20D19D18D17D16Data 1D15D14D13D12Data 2D11D10D9D8Data 3D7D6D5D4Data 4D3D2D1D0AddressD23 to D20D19D18D17D16Data 1D15D14D13D12Data 2D11D10D9D8Data 3D7D6D5D4Data 4D3D2D1D0Command Preset Table ($34FX to 3FX)—: Don’t care – 24 – CXD2545Q Auto sequenceBlind (A, E),Brake (B),Overflow (C, D)Sled kick, brake (D), Kick (F)Auto sequence (N) track jump count settingMODE settingFunction specificationAudio CTRLTraverse monitor counter settingSpindle servo coefficient settingCLV CTRLCLV MODE0 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 0000001000000110000010000100010100011001100000000000000000000000000000000000000001000100000000000000000000000000000000000000000000000———0———0——————0———0——————0———0——————0———0———————————————————————————————————————————————456789ABCDERegisterCommandAddressD23 to D20Data 1D19D18D17D16Data 2D15D14D13D12Data 3D11D10D9D8Data 4D7D6D5D4Data 5D3D2D1D0Command Preset Table ($4X to EX)—: Don’t care – 25 – CXD2545Q <Coefficient ROM Preset Values Table (1)> ADDRESS K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F E0 81 23 7F 6A 10 14 30 7F 46 81 1C 7F 58 82 7F SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F 4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix∗ TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L 82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00 TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED DATA CONTENTS – 26 – CXD2545Q <Coefficient ROM Preset Values Table (2)> ADDRESS K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B K3C K3D K3E K3F 80 66 00 7F 6E 20 7F 3B 80 44 7F 77 86 0D 57 00 Fix∗ ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED K40 K41 K42 K43 K44 K45 K46 K47 K48 K49 K4A K4B K4C K4D K4E K4F 04 7F 7F 79 17 6D 00 00 02 7F 7F 79 17 54 00 00 TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN NOT USED NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED DATA CONTENTS ∗ Fix indicates that normal preset values should be used. – 27 – CXD2545Q §1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) $0X $1X $2X $38 $38 $30 to 37, $3A to 3F $3904 $3908 $390C $391C $391D $391F $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X, DX, FX Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z GFS COMP COUT OV64 Z FZC AS TZC AGOK∗ 1 XAVEBSY∗ 1 SSTP TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. XBUSY FOK 0 GFS COMP COUT OV64 0 — — — — — — 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit — — — — — — — — ASEQ = 0 ASEQ = 1 Output data length ∗ 1 $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. – 28 – CXD2545Q Description of SENS Signals The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with Reg B. High when Reg B is latched, low when the initial Reg B number is input by CNIN. Counts the number of tracks set with Reg B. High when Reg B is latched, toggles each time the Reg B number is input by CNIN. While $44 and $45 are being executed, toggles with each CNIN 8-count instead of the Reg B number. Low when the EFM signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. Z XBUSY FOK GFS COMP COUT OV64 SENS output – 29 – CXD2545Q  Description of CD Signal Processing-System Commands and Functions §2-1. Description of Commands and Data Sets $4X commands Register name 4 Data 1 Data 2 Data 3 Command AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0 0 0 MAX timer value Timer range Command Cancel Fine Search Focus-On 1 Track Jump 10 Track Jump 2N Track Jump M Track Move 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 RXF 1 RXF RXF RXF RXF AS3 AS2 AS1 AS0 RXF = 0 Forward RXF = 1 Reverse • When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. • When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted. • To invalidate the MAX timer, set $4X0 and the timer value to 0. $5X commands Timer TR3 TR2 TR1 TR0 Blind (A, E), Overflow (C, G) Brake (B) 0.18ms 0.36ms 0.09ms 0.18ms 0.045ms 0.09ms 0.022ms 0.045ms Cancel timer value MT3 23.2ms 1.49s MT2 11.6ms 0.74s MT1 5.8ms 0.37s MT0 2.9ms 0.18s LSSL 0 1 0 0 0 0 0 0 0 0 0 Timer range – 30 – CXD2545Q Register name 6 Data 1 Data 2 KICK (D) SD3 SD2 SD1 SD0 KF3 KF2 KF1 KF0 KICK (F) $6X commands Timer SD3 SD2 SD1 SD0 When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D 23.2ms 11.6ms 11.6ms 5.8ms 5.8ms 2.9ms 2.9ms 1.45ms Timer KF3 KF2 KF1 KF0 KICK (F) 0.72ms 0.36ms 0.18ms 0.09ms Command Data 1 Data 2 Data 3 Data 4 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 Auto sequence track jump count setting This command is used to set N when a 2N-track jump is executed, M when an M track move is executed and the jump count when a fine search is executed for auto sequence. • The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count is determined by the mechanical limitations of the optical system. • When the track jump count is from 0 to 15, the COUT signal is used to count tracks for 2N-track jump/M track move; when the count is 16 or over, the MIRR signal is used. For fine search, the COUT signal is used to count tracks. $8X commands $7X commands Auto sequence track jump count setting Command MODE specification CDROM DOUT Mute D.out Mute-F WSEL D19 Data 1 Data 2 D18 D17 D16 VCO SEL ASHS SOCT 0 D15 D14 D13 D12 Command bit C2PO timing CDROM = 1 CDROM = 0 See the Timing Chart 2-1. See the Timing Chart 2-1. CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing Command bit DOUT Mute = 1 DOUT Mute = 0 When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted. Processing Command bit D. out Mute F = 1 D. out Mute F = 0 When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off. Processing – 31 – CXD2545Q Command bit Sync protection window width WSEL = 1 WSEL = 0 ±26 channel clock∗ ±6 channel clock Anti-rolling is enhanced. Sync window protection is enhanced. Application ∗ In normal-speed playback, the channel clock=4.3218MHz ∗ See mute conditions (1), (2) and (4) to (6) under $AX commands for other mute conditions. MD2 Other mute conditions∗ DOUT Mute D.out Mute F DOUT output off 0dB –∞dB DA output 0dB 0dB –∞dB 0dB –∞dB –∞dB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Command bit Processing VCOSEL = 0 VCOSEL = 1 The built-in VCO is set to normal speed. The built-in VCO is set to high speed. Used for normal-speed and double-speed (double correction) playback. Used for quadruple-speed and double-speed (quadruple correction) playback. Use Command bit Function ASHS = 0 ASHS = 1 The command transfer rate to SSP is set to normal speed. The command transfer rate to SSP is set to half speed. Used for normal-speed and double-speed (double correction) playback. Used for quadruple-speed and double-speed (quadruple correction) playback. Use Command bit Function SOCT = 0 SOCT = 1 Sub Q is output from the SQSO pin. Each signal is output from the SQSO pin. Input the readout clock to SQCK. (See the Timing Chart 2-11.) – 32 – CXD2545Q Command Data 1 Function specification DCLV ON-OFF DSPB ON-OFF A.SEQ ON-OFF D.PLL ON-OFF D19 D18 D17 D16 Data 2 BiliGL MAIN BiliGL SUB FLFC D15 D14 D13 0 D12 $9X commands Command bit DCLV on/off=0 During CLVS mode FSW = low, MON = high, MDS = Z; MDP = servo control signal, carrier frequency of 230Hz at TB = 0 and 460Hz at TB = 1. FSW = Z, MON = high; MDS = speed control signal, carrier frequency of 7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz. When DCLV, PWM and MD = 1 MDS = PWM polarity signal, carrier frequency of 132kHz MDP = PWM absolute value output (binary), carrier frequency of 132kHz When DCLV, PWM and MD = 0 MDS = Z MDP = ternary PWM output, carrier frequency of 132kHz During CLVP mode During CLVS and CLVP modes DCLV on/off = 1 (FSW, MON not required) CLV mode Contents When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches simultaneously with the CLVP/CLVS switching. Therefore, the cut-off frequency for the CLVS is fc = 70Hz at TB = 0, and fc = 140Hz at TB = 1. Command bit DSPB = 0 DSPB = 1 Normal-speed playback, C2 error quadruple correction, variable pitch possible. Double-speed playback, C2 error double correction, variable pitch prohibited. Processing Normally, FLFC is 0. Command bit DPLL = 0∗ DPLL = 1 RFPLL is analog. PDO, VCOI and VCOO are used. RFPLL is digital. PDO is high impedance. Meaning ∗ External parts for Pins 18 to 20 are required even when analog PLL is selected. Command bit BiliGL SUB = 0 BiliGL SUB = 1 STEREO SUB MAIN Mute BiliGL MAIN = 0 BiliGL MAIN = 1 Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO. – 33 – CXD2545Q Command Data 1 Audio CTRL Vari Up Vari Down Mute ATT D19 D18 D17 D16 Data 2 PCT1 PCT2 D15 D14 0 D13 0 D12 $AX commands Vari Up Vari Down Pitch X’tal 0% VCO 0% +0.1% +0.2% +0.3% +0.2% +0.1% +0% –0.1% –0.2% X'tal 0% Command bit Mute = 0 Mute = 1 Mute off if other mute conditions are not set. Mute on. Peak register reset. Meaning Command bit ATT = 0 ATT = 1 Attenuation off –12dB Meaning Mute conditions (1) When register A mute = 1. (2) When Mute pin = 1. (3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1). (4) When GFS stays low for over 35ms (during normal-speed). (5) When register 9 BiliGL MAIN = Sub = 1. (6) When register A PCT1 = 1 and PCT2 = 0. (1) to (4) perform zero-cross muting with a 1 ms time limit. Command bit PCT1 0 0 1 1 PCT2 0 1 0 1 Normal mode Level meter mode Peak meter mode Normal mode × 0dB × 0dB Mute × 0dB C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Meaning PCM Gain ECC error correction ability Description of level meter mode (see the Timing Chart 2-2.) • When the LSI is set to this mode, it can possess digital level meter functions. • When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits of data are Sub Q data (see §2-2. Subcode Interface). The last 16 bits are LSB first, 15-bit PCM data (absolute values). The final bit is PCM data. However, it is high when generated by the left channel and low when generated by the right channel. • PCM data is reset and the L/R flag is reversed after one readout. The maximum value for this status is then measured until the next readout. – 34 – CXD2545Q Description of peak meter mode (see the Timing Chart 2-3.) • When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. • When the 96-bit clock is input, 96 bits of data are output to SQSO and the LSI internal register is reset. In other words, the PCM maximum value detection register is not reset by the readout. • To reset the PCM maximum value detection register, set PCT1 = PCT2 = 0 or set the $AX mute. • The Sub Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. The normal operation is conducted for the relative time. • The final bit (L/R flag) of the 96-bit data is normally 0. • The pre-value hold and average value interpolation data are fixed to level (–∞) for this mode. $BX commands This command sets the traverse monitor count. Servo coefficient setting CLV CTRL ($DX) Gain MDP1 Gain MDP0 Gain MDS1 Gain MDS0 Gain CLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS –12dB –6dB –6dB 0dB 0dB +6dB Command D19 Data 1 Data 2 D18 D17 D16 0 Gain DCLV0 0 0 D15 D14 D13 D12 Explanation Valid only when DCLV = 1. Valid when DCLV = 1 or 0. The spindle servo gain is externally set when DCLV = 1. • CLVS mode gain setting: GCLVS Note) When DCLV = 0, the CLVS gain is as follows: When Gain CLVS = 0, GCLVS = –12dB. When Gain CLVS = 1, GCLVS = 0dB. Command Data 1 Data 2 Data 3 Data 4 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 Traverse monitor count setting • When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. • The traverse monitor count is set when the traverse status is monitored by the SENS output COMP and COUT. $CX commands – 35 – CXD2545Q Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP –6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS –6dB 0dB +6dB • CLVP mode gain setting: GMDP: GMDS Gain DCLV0 0 1 GDCLV 0dB +6dB • DCLV overall gain setting: GDCLV $DX commands See the $CX commands. Note) Peak hold is performed at 34kHz in CLVH mode. CLV CTRL DCLV PWM MD TB TP Gain CLVS Command D19 D18 D17 D16 Command bit DCLV PWM MD = 1 DCLV PWM MD = 0 Digital CLV PWM mode specified. Both MDS and MDP are used. Digital CLV PWM mode specified. Ternary MDP values are output. Explanation (See the Timing Chart 2-4.) Command bit TB = 0 TB = 1 TP = 0 TP = 1 Bottom hold in CLVS and CLVH modes at a cycle of RFCK/32. Bottom hold in CLVS and CLVH modes at a cycle of RFCK/16. Peak hold in CLVS mode at a cycle of RFCK/4. Peak hold in CLVS mode at a cycle of RFCK/2. Explanation – 36 – CXD2545Q $EX commands STOP: Spindle motor stop mode KICK: Spindle motor forward rotation mode BRAKE: Spindle motor reverse rotation mode CLVS: Rough servo mode. When the RF-PLL circuit lock is disengaged, this mode is used to pull the disc rotations within the RF-PLL capture range. CLVP: PLL servo mode CLVA: Automatic CLVS/CLVP switching mode. This mode is normally used during playback. CLV mode CM3 CM3 0 1 1 1 1 1 0 CM2 0 0 0 1 1 1 1 CM1 0 0 1 1 0 1 1 CM0 0 0 0 0 0 1 0 Mode STOP KICK BRAKE CLVS CLVH CLVP CLVA Explanation See the Timing Chart 2-5. See the Timing Chart 2-6. See the Timing Chart 2-7. Command D19 CM2 D18 CM1 D17 CM0 D16 – 37 – CXD2545Q Timing Chart 2-1Rch 16bit C2 PointerLch 16bit C2 PointerIf C2 Pointer = 1,data is NGC2 Pointer for upper 8bitsC2 Pointer for lower 8bitsRch C2 PointerC2 Pointer for upper 8bitsC2 Pointer for lower 8bitsLch C2 PointerLRCKWDCKCDROM = 0C2POCDROM = 1C2PO48 bit slot – 38 – CXD2545Q Timing Chart 2-296 clock pulsesWFCK12396 clock pulsesCRCFCRCF123Peak data of this section16 bitR/LL/R96 bit dataHold section123808196CRCFSQCKD0D1D2D3D4D5D6D13D14L/RPeak dataL/R flagSub-Q DataSee "Sub Code Interface"15-bit peak dataAbsolute value display, LSB first750ns to 120µsSQCKSQSOSQSOLevel Meter Timing – 39 – CXD2545Q Timing Chart 2-3Measurement96 clock pulsesCRCFWFCK123MeasurementMeasurement96 clock pulsesCRCFCRCF123SQCKPeak Meter Timing – 40 – CXD2545Q Timing Chart 2-4 Timing Chart 2-5 MDS MDP DCLV PWM MD = 0 Z Acceleration 132kHz 7.6µs n · 236 (ns) n = 0 to 31 Deceleration Z DCLV PWM MD=1 MDS 7.6µs Acceleration n · 236 (ns) n = 0 to 31 Deceleration MDP Output Waveforms with DCLV = 1 MDS MDP STOP Z Z L DCLV = 0 STOP MDS Z DCLV = 1 DCLV PWM MD = 0 FSW and MON are the same as for DCLV = 0 MDP FSW MON L L – 41 – CXD2545Q DCLV = 1 DCLV PWM MD = 1 STOP MDS L MDP FSW and MON are the same as for DCLV = 0 Timing Chart 2-6 H DCLV = 0 KICK MDS Z H H KICK MDS Z H DCLV = 1 DCLV PWM MD = 0 Z 7.6µs H L KICK DCLV = 1 DCLV PWM MD = 1 MDS MDP FSW MON MDP MDP FSW and MON are the same as for DCLV = 0 L FSW and MON are the same as for DCLV = 0 – 42 – CXD2545Q Timing Chart 2-7 DCLV = 1 DCLV PWM MD = 1 MDS L BRAKE MDS Z DCLV = 1 DCLV PWM MD = 0 Z MDP MDP L DCLV = 0 BRAKE MDS Z H MDP FSW MON L FSW and MON are the same as for DCLV = 0 FSW and MON are the same as for DCLV = 0 L H L – 43 – CXD2545Q §2-2. Subcode Interface This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK. Sub Q can be read out after the CRC check of the 80 bits of information in the subcode frame. This is accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data from the SQSO pin. P to W Subcode Read Data can be read out by inputting EXCK immediately after WFCK falls. (See the Timing Chart 2-8.) 80-bit Sub Q Read Fig. 2-9 shows the peripheral block of the 80-bit Sub Q register. • First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. • 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. • In the CXD2545Q, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. • Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read. In this LSI, the SQCK input is detected, and the retriggerable monostable multivibrator for low is reset. • The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the S/P register is not loaded into the P/S register. • While the monostable multivibrator is being reset, data cannot be loaded into the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant, the register will not be rewritten by CRCOK and others. • In this LSI, the previously mentioned peak detection register can be connected to the shift-in of the 80-bit P/S register. Input and output for ring control 1 are shorted in peak meter or level meter mode. Those for ring 2 are shorted in peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode. • In addition, as previously mentioned, the absolute time after peak is generated is stored in the memory in peak meter mode. (See the Timing Chart 2-10.) • Although a clock is input from the SQCK pin to actually perform these operations, the high and low intervals for this clock should be between 750ns and 120µs. – 44 – CXD2545Q Timing Chart 2-8 Internal PLL clock 4.3218 ±∆MHz WFCK SCOR EXCK SBSO 750ns max S0 · S1 Q R WFCK SCOR EXCK SBSO S0•S1 Q R S T U V W S0•S1 P1 Q R S T U V W P1 P2 P3 Same Same Subcode P.Q.R.S.T.U.V.W Read Timing – 45 – CXD2545Q Block Diagram 2-9888888888OrderInversion16Peak detectionLOAD CONTROLRing control 2CRCFMixMonostablemultivibratorCRCCABS time load controlfor peak value16 bit P/S registerRing control 1SOSISQSOSQCKSHIFTSHIFTSUBQ LDLDSOHGFEDCBAABCDEFGHSI80 bit P/S Register80 bit S/P Register(AFRAM)(ASEC)(AMIN)ADDRS CTRLSINSUBQLDLDLDLDLDLDLD – 46 – CXD2545Q Timing Chart 2-101239192939495969798WFCKSCORSQSOSQCKMonostableMultivibrator (Internal)CRCF1Determined by modeCRCF280 or 96 ClockRegister load forbidder270 to 400µs when SQCK = high.750ns to 120µs300ns maxCRCFADR0ADR1ADR2ADR3CTL0CTL1CTL2CTL3SQCKSQSO123CRCF1 – 47 – CXD2545Q PER1XLATSQCKExample: $802 latchSet SQCK and EXCK high during this interval.Internal signal latch750ns or morePER0PER2PER3PER4PER5PER6PER7C1F0C1F1C1F2C2F0C2F1C2F2FOKGFSLOCKEMPHSQSOTiming Chart 2-11SignalPER0 to PER7∗FOKGFSLOCKEMPHRF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.Focus OKHigh when the frame sync and the insertion protection timing match.GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low.Outputs a high signal when the playback disc has emphasis.ExplanationC1F2000011110011001101010101No C1 errors;C1 pointer resetOne C1 error corrected;C1 pointer reset——No C1 errors;C1 pointer setOne C1 error corrected;C1 pointer setTwo C1 errors corrected;C1 pointer setC1 correction impossible;C1 pointer setC1F1C1F0DescriptionC2F2000011110011001101010101No C2 errors;C2 pointer resetOne C2 error corrected;C2 pointer resetTwo C2 errors corrected;C2 pointer resetThree C2 errors corrected;C2 pointer resetFour C2 errors corrected;C2 pointer reset—C2 correction impossible;C1 pointer copyC2 correction impossible;C2 pointer setC2F1C2F0Description∗RF jitter amount PER0 to PER7 are output in binary code. When the RF jitter amount is small, the correlation is such that the binary code numberdecreases. – 48 – CXD2545Q §2-3. Digital PLL • The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 2-12. The CXD2545Q has a built-in three-stage PLL. • The first-stage PLL regenerates the variable pitch. LPF and VCO are necessary as external parts. The minimum variable amount of pitch is 0.1%. The output of this first-stage PLL is used as a reference for all clocks within the LSI. Input the XTAO output to the VCKI pin when variable pitch is not used. • The second-stage PLL regenerates a high-frequency clock needed by the third-stage digital PLL. • The third-stage PLL is a digital PLL that regenerates the actual channel clock, and has a ±150kHz (normal- speed playback) or more capture range. – 49 – CXD2545Q Block Diagram 2-12 OSC Vari-Pitch 1/4 1/1000 1/4 1/1000 + n Phase comparatorUp down counter n = –217 to +168 X'tal Microcomputer control VPCO LPF VCO 19.78 to 13.26MHz VCKI Phase comparatorDigital PLL I/M I/N 2/1 MUX PCO FILI FILO CLTV VCO RFPLL CXD2545Q VDD (384Fs) 16.9344MHz XTSL Vari-Pitch – 50 – CXD2545Q §2-4. EFM Frame Sync Protection • In a CD player operating at normal speed, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. • In the CXD2545Q, window protection and forward protection/backward protection have been adopted for frame sync protection. The adoption of these functions achieves very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. In other words, when the frame sync is being regenerated normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window is released and the frame sync is resynchronized. In addition, immediately after the window is released and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window is released immediately. §2-5. Error Correction • In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte C2 parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. • The CXD2545Q uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. • In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the generation status of the EFM signal, and the operating status of the player. • The correction status can be monitored outside the LSI. See the Table 2-13. • When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 No C1 errors; C1 pointer reset One C1 error corrected; C1 pointer reset — — No C1 errors; C1 pointer set One C1 error corrected; C1 pointer set Two C1 errors corrected; C1 pointer set C1 correction impossible; C1 pointer set No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset — C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set MNT2 MNT1 MNT0 Description Table 2-13. – 51 – CXD2545Q Timing Chart 2-14 Normal-speed PB 400 to 500ns RFCK MNT3 MNT1 MNT0 t = Dependent on error condition C1 correction C2 correction Strobe Strobe MNT2 §2-6. DA Interface • The CXD2545Q has two modes as DA interfaces. a) 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. b) 64-bit slot interface This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first. When LRCK is low, the data is for the left channel. – 52 – CXD2545Q Timing Chart 2-15LRCK(44.1K)DA15(2.12M)WDCKDA16LRCK(88.2K)DA15(4.23M)WDCKDA1648bit slot Normal-Speed Playback PSSL = L124R0Lch MSB (15)L14L13L12L11L10L9L8L7L6L5L4L3L2L1L0RMSBLch MSB (15)24Rch MSB2345678910111248bit slot Double-Speed Playback12L0R0 – 53 – CXD2545Q Timing Chart 2-161234567891011121314R15Lch LSB (0)Rch LSB (0)12345678910111213141520303231DA12(44.1K)DA13(2.82M)DA1464 Bit slot Normal Speed PB PSSL = L1Lch LSB12345101525DA12(88.2K)DA13(5.64M)DA1464 Bit slot Double- Speed PB20303132Rch LSB (0)23567891011121314154L15 – 54 – CXD2545Q §2-7. Digital Out There are three digital output formats; the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2545Q supports Type 2 form 1. Regarding the clock accuracy of the channel status, level III is set automatically when the crystal clock is used and level II is variable pitch. In addition, Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3). DOUT is output when the crystal is 34 MHz, the variable pitch is reset, and DSPB = 1. Therefore, set MD2 to 0 and turn DOUT off. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 ID0 ID1 COPY Emph 0 0 0 0 1 0 0 0 0 0 0 0 From sub-Q 0 16 32 48 176 ......Sub Q control bits that matched twice with CRCOK Digital Out C bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ......Varipitch: 1 X'tal: 0 bit0 to 3 bit29 Table 2-17. §2-8. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1 track jump, 2N track jumps, fine search, and M track move are executed automatically. The servo block is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the servo block, but can be sent to the signal processor block. In addition, when using the auto sequencer, turn the A.SEQ of register 9 on. When the clock goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is designed to prevent the transfer of erroneous data to the servo block when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (When XBUSY is low). – 55 – CXD2545Q In addition, a MAX timer is built-in as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See 2-1, $4X commands concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range should be actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 2-18. The auto focus is executed after focus search-up, and the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. – 56 – CXD2545Q Auto focus Focus search up FOK = H NO YES FZC = H NO YES FZC = L NO YES END Focus servo ON Check whether FZC is continuously high for the period of time E set with register 5. Fig. 2-18 (a). Auto Focus Flow Chart XLAT $47 Latch $03 Blind E $08 FOK SEIN (FZC) BUSY Command for SSP Fig. 2-18 (b). Auto Focus Timing Chart – 57 – CXD2545Q (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use them when focus, tracking, and sled servo are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not performed. • 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 2-19. Set blind A and brake B with register 5. • 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 2-20. The principal difference between the 10-track jump and the 1-track jump is whether to kick the sled or not. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set in register 5), the tracking and sled servos are turned on. • 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 2-21. The track jump count "N" is set in register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used with N is 16 or higher. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6. • Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 2-22. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and long jumps are possible by controlling the sled. The track jump count is set in register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F in register 5. In addition, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls in register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set in register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N – α for the traverse monitor counter which is set in register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset. • M track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M track move is performed in accordance with Fig. 2-23. M can be set to 216 tracks. COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or higher. The M track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servo are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 after the actuator is stabled. – 58 – CXD2545Q 1 Track NO YES END Track kick sled servo WAIT (Blind A) COUT = Track REV kick WAIT (Brake B) Track sled servo ON REV kick for REV jump FWD kick for REV jump Fig. 2-19 (a). 1-Track Jump Flow Chart XLAT COUT BUSY $48 (REV = $49) Latch $28 ($2C) Blind A Brake B $2C ($28) $25 Command for SSP Fig. 2-19 (b). 1-Track Jump Timing Chart – 59 – CXD2545Q 10 Track NO YES END Track, sled FWD kick WAIT (Blind A) COUT = 5 ? Track, REV kick Track, sled servo ON Check whether the COUT cycle is longer than overflow C. Counts COUT × 5 NO YES C = Over-flow ? Fig. 2-20 (a). 10-Track Jump Flow Chart COUT $4A (REV = $4B) Latch Blind A $2A ($2F) COUT 5 count $2E ($2B) Over-flow C $25 XLAT BUSY Command for SSP Fig. 2-20 (b). 10-Track Jump Timing Chart – 60 – CXD2545Q 2N Track NO YES END Track, sled FWD kick WAIT (Blind A) COUT (MIRR) = N Track REV kick Track servo ON NO YES C = Over-flow WAIT (Kick D) Sled servo ON Counts COUT till N < 16. Counts MIRR till N ≥ 16. Fig. 2-21 (a). 2N-Track Jump Flow Chart XLAT Blind A $2A ($2F) COUT (MIRR) N count $2E ($2B) Over-flow C Kick D $26 ($27) $25 $4C (REV = $4D) Latch COUT (MIRR) BUSY Command for SSP Fig. 2-21 (b). 2N-Track Jump Timing Chart – 61 – CXD2545Q Track Servo ON Sled FWD Kick Fine Search WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Over-flow G) COUT = N ? Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END YES NO Fig. 2-22 (a). Fine Search Flow Chart Traverse Speed Control (Over-flow G) & COUT N count $44 (REV = $45) Latch Kick D Kick F Kick D $26 ($27) $2A ($2F) $27 ($26) $25 XLAT COUT BUSY Fig. 2-22 (b). Fine Search Timing Chart – 62 – CXD2545Q M Track Move NO YES END Track Servo OFF Sled FWD Kick WAIT (Blind A) COUT (MIRR) = M Track, Sled Servo ON Counts COUT till N < 16. Counts MIRR till N ≥ 16. Fig. 2-23 (a). M-Track Move Flow Chart XLAT Blind A $22 ($23) COUT (MIRR) M count $20 $4E (REV = $4F) Latch COUT (MIRR) BUSY Command for servo Fig. 2-23 (b). M-Track Move Timing Chart – 63 – CXD2545Q §2-9. Digital CLV Fig. 2-24 shows the block diagram. Digital CLV makes PWM output in CLVS, CLVP and other modes with the MDS error or MDP error signal sampling frequency increased to 130kHz during normal-speed operation. In addition, the digital spindle servo can set the gain. Digital CLV CLVS U/D MDS Error MDP Error CLV-P/S Measure Measure 2/1 MUX Over Sampling Filter-1 CLV P CLV S 1/2 Mux CLV-P/S Over Sampling Filter-2 Noise Shape Modulation KICK, BRAKE STOP DCLVMD MDP MDS Mode Select Gain MDP Gain MDS Gain CLVS Gain DCLV Fig. 2-24. Block Diagram CLVS U/D: Up/down signal from the CLV-S servo MDS error: Frequency error for the CLV-P servo MDP error: Phase error for the CLV-P servo – 64 – CXD2545Q §2-10. Asymmetry Compensation Fig. 2-25 shows the block diagram and circuit example. ASYE RFAC R1 R1 R1 2 R2 5 = BIAS R1 R1 R2 CXD2545Q 42 36 37 39 38 ASYO ASYI Fig. 2-25. Example of an Asymmetry Compensation Application Circuit §2-11. Playback Speed In the CXD2545Q, the following playback modes can be selected through different combinations of the crystal, XTSL pin, double-speed playback command (DSPB), VCO selection command (VCOSEL) and command transfer rate selector (ASHS). Also, the minimum operating voltage changes according to the playback mode. (See the Recommended Operating Conditions.) Playback modes Mode 1 2 3 4 5 6 7 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs 1 1 0 0 0 0 1 0 1 0 1 0 1 1 0/1 0/1 1 1 0/1 0/1 0/1 0 0 1 1 0 0 0 × 1 × 2 × 2 × 4 × 1 × 2 × 1 C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double X'tal XTSL DSPB VCOSEL ASHS Playback speed Error correction However, Fs = 44.1kHz. – 65 – CXD2545Q  Description of Servo Signal Processing-System Functions and Commands §3-0. General Description of the Servo Signal Processing System (Voltages are the values for a 5V power supply.) Focus servo Sampling rate: 88.2kHz Input range: 2.5V center ±1.0V Output format: 7-bit PWM Others: Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Automatic gain control Tracking servo Sampling rate: 88.2kHz Input range: 2.5V center ±1.0V Output format: 7-bit PWM Others: Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Automatic gain control Vibration countermeasure Sled servo Sampling rate: 345Hz Input range: 2.5V center ±1.0V Output format: 7-bit PWM Other: Sled move FOK, MIRR, DFCT signals generation RF signal sampling rate: 1.4MHz Input range: 2.15V to 5.0V Others: RF zero level automatic measurement The signal input from the RFDC pin is multiplied by a factor of 0.7 and loaded into the A/D converter. – 66 – CXD2545Q §3-1. Digital Servo Block Master Clock (MCK) The FSTI pin (Pin 66) is the reference clock input pin. The internal master clock (MCK) is generated by dividing the frequency of the signal input to FSTI. the frequency division ratio is 1/2 or 1/4. Table 3-1 below shows the hypothetical case where the crystal clock generated from the digital signal processor block is 2/3 frequency divided and input to the FSTI pin (Pin 66) by externally connecting the FSTI pin (Pin 66) and the FSTO pin (Pin 67). The XT4D and XT2D command settings can be made with D13 and D12 of $3F. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz. Mode 1 2 3 4 384Fs 384Fs 768Fs 768Fs 256Fs 256Fs 512Fs 512Fs 256Fs 256Fs 512Fs 512Fs ∗ 0 ∗ 1 0 0 1 0 1 0 0 0 1/2 1/2 1/4 1/4 128Fs 128Fs 128Fs 128Fs X'tal FSTO FSTI XTSL XT4D XT2D Frequency division ratio MCK frequency Fs = 44.1kHz, ∗ : Don’t care Table 3-1. §3-2. AVRG (Average) Measurement and Compensation The CXD2545Q has a compensation circuit which performs compensation using the RFDC, VC, FE and TE AVRG measurement circuits and their measurement results in order to perform reliable servo control. AVRG measurement and compensation is necessary to initialize the CXD2545Q, and can cancel the offset by performing each AVRG measurement before playback operation and using these results for compensation. The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VLCM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38 respectively to 1. AVRG measurement consists of digitally measuring the level applied to each analog input pin by taking the average of 256 samples, and then loading these values into the AVRG register. AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received. During AVRG measurement, if the upper 8 bits of the serial data are 38 (Hex), the termination of AVRG measurement operation can be confirmed by monitoring the SENS pin (Pin 80). (See the Timing Chart 3-2.) XLAT SENS (= XAVEBSY) Max. 1µs Termination of AVRG measurement 2.9 to 5.8ms Timing Chart 3-2. – 67 – CXD2545Q <Measurement> • VC AVRG The offset can be canceled by measuring the VC level which is the center potential for the system and using that value to apply compensation to each input error signal. • FE AVRG This measures the FE signal DC level. In addition, compensation is applied to the FZC comparator level output from the SENS pin during FCS SEARCH (focus search) using these measurement results. • TE AVRG This measures the TE signal DC level. • RF AVRG The CXD2545Q generates the MIRR, DFCT and FOK signals from the RF signal. However, the FOK signal is generated by comparing the RF signal at a certain level, so that it is necessary to establish a zero level which becomes the comparator level reference. Therefore, the RF signal is measured before playback operation, and compensation applied to bring this level to the zero level. An example of sending AVRG measurement and compensation commands is shown below. (Example) $380800 (RF Avrg. measurement on) $382000 (FE Avrg. measurement on) $380010 (TE Avrg. measurement on) $388000 (VC Avrg. measurement on) (Finish each AVRG measurement before starting the next.) $38140A (RFLC, FLC0, FLC1 and TLC1 commands on) (The required compensation turn on together; see Fig. 3-3.) An interval of 5.8ms or more must be maintained between each command, or the SENS pin must be monitored and the next AVRG command sent after confirming that the previous command has been finished. <Compensation> See Fig. 3-3 for the contents of each compensation below. • RFLC The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register. (00 is input when the RF signal is lower than the RF AVRG value.) • TCL0 The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register. • TCL1 The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register. • VCLC The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register. • FLC1 The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register. • FLC0 The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register. – 68 – CXD2545Q §3-3. E:F Balance Adjustment Function When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-band component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-band component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 applies only the amount of compensation (subtraction) equal to the TRVSC register value to the values obtained from the TE and SE input pins, enabling the E:F balance offset to be adjusted. (See Fig. 3-3.) §3-4. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 3-3.) When the FBIAS register value is set to D11 = 0 and D10 = 1 by $34F, data can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See the CD Signal Processing-System Block Timing Chart 2-4.) – 69 – CXD2545Q TE AVRGregisterTLC1TRVSCregisterTLC2––To TRK/SLD In registerVC AVRGregisterTLC0–VCLC–TE, SE from A/DFE AVRGregisterFLC1FBIASregisterFBON––To FCS In registerFLC0To FZC registerFE from A/D–RFLC–To RF In registerRFDC from A/DRF AVRGregisterFig. 3-3. – 70 – CXD2545Q §3-5. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the input serial data are 38 (Hex), the termination of AGCNTL operation can be confirmed by monitoring the SENS pin (Pin 80). (See the Timing Chart 3-4 and the Description of SENS Signals.) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) When performing AGCNTL operation, each servo filter must be in the gain normal status, and the anti- shock circuit (described hereafter) must be disabled. XLAT SENS (= AGOK) Max. 11.4µs AGCNTL termination Timing Chart 3-4. Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has terminated, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during high sensitivity adjustment) AGV2; AGCNTL sensitivity 2 (during low sensitivity adjustment) AGHS; High sensitivity adjustment on/off AGHT; High sensitivity adjustment time Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. – 71 – CXD2545Q AGCNTL and default operation have two stages. In the first stage, high sensitivity adjustment is performed for a certain period of time (select 256/128ms with AGHT), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is led reliably towards the appropriate value at a relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2545Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ), and then terminates AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by rewriting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation and the relationship between the various settings are shown in Fig. 3-5. Initial value SENS AGCNTL Start AGCNTL completion Convergence value AGCNTL coefficient value Slope AGV1 AGHT AGJ Slope AGV2 Fig. 3-5. – 72 – CXD2545Q §3-6. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 3-6.) Register name Command D23 to D20 D19 to D16 1 0 ∗ ∗ 1 1 ∗ ∗ 0 ∗ 0 ∗ 0 ∗ 1 ∗ 0 ∗ 1 0 0 ∗ 1 1 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP 0 0 0 0 FOCUS CONTROL 0 Table 3-6. FCS Search FCS search is required in the course of turning on the FCS servo. Figs. 3-7 and 3-8 show the signals for sending commands $00 → $02 → $03 and performing only FCS search operation, and for moving from $03 to FCS on ($08). FCSDRV RF FOK FE FZC FZC comparator level $00 $02 $03 0 0 FCSDRV RF FOK FE FZC $00 $02 $03 0 $08 Fig. 3-7. Fig. 3-8. ∗ : Don’t care – 73 – CXD2545Q §3-7. TRK (Tracking) and SLD (Sled) Servo Control TRK and SLD servo control is performed by the 8-bit command $2X. (See Table 3-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin. 0 0 ∗ ∗ 0 1 ∗ ∗ 1 0 ∗ ∗ 1 1 ∗ ∗ ∗ ∗ 0 0 ∗ ∗ 0 1 ∗ ∗ 1 0 ∗ ∗ 1 1 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE 0 0 1 0 TRACKING MODE 2 Table 3-9. TRK Servo The TRK JUMP (track jump) height can be set with the 6 bits D13 to D8 of $36. In addition, when the TRK servo is on, the TRK servo filter assumes gain-up status when D17 of $1 is set to 1. The TRK servo filter also assumes gain-up status when vibration detection is performed with the LOCK signal (Pin 98) low and the anti-shock circuit (described hereafter) enabled. The gain-up filter used when TRK has assumed gain up status has two types of structures which can be selected by setting D16 of $1. (See Table 3-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from the 6 bits D13 to D8 of $37, is determined by multiplying this value by the × 1, × 2, × 3 or × 4 magnification set using D17 and D16 when D19 = D18 = 0 is set with $3. (See Table 3-10.) SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the operations which set the TRK servo to gain up status and turn off the SLD servo can be canceled by setting D6 (LKSW) of $38 to 1. 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 SLED KICK LEVEL (basic value × ±1) SLED KICK LEVEL (basic value × ±2) SLED KICK LEVEL (basic value × ±3) SLED KICK LEVEL (basic value × ±4) 0 0 1 1 SELECT 3 Table 3-10. ∗ : Don’t care Register name Command D23 to D20 D19 to D16 Register name Command D23 to D20 D19 to D16 – 74 – CXD2545Q §3-8. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin (Pin 26) is sampled at approximately 1.4MHz and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of these envelope waveforms. The MIRR signal is generated by comparing this MIRR comparator level with the waveform generated by subtracting the bottom hold value from the peak hold value. (See Fig. 3-11.) RF Peak Hold Bottom Hold Peak Hold – Bottom Hold MIRR MIRR Comp (Mirror comparator level) H L RF Peak Hold1 Peak Hold2 Peak Hold2 – Peak Hold1 DFCT (Defect comparator level) H L SDF Fig. 3-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 3-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. Fig. 3-12. – 75 – CXD2545Q §3-9. DFCT Countermeasure Circuit The DFCT countermeasure circuit performs operations to maintain the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by performing scratch and defect detection with the DFCT signal generation circuit, and when DFCT goes high, applying the low frequency element of the error signal before DFCT went high to the FCS and TRK servo filter inputs. In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1 or by inputting high level to the DFSW pin (Pin 84). Input register Hold register Hold Filter Servo Filter EN Error signal DFCT Fig. 3-13. §3-10. Anti-Shock Circuit When vibrations are produced in the CD player, this circuit forces the TRK filter to assume gain-up status so that the servo does not become easily dislocated. This circuit should be considered for systems which require vibration countermeasures. Specifically, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 3-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level can essentially be adjusted by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 3-17.) This circuit can also support an external vibration detection circuit, and can also set the TRK servo filter to gain up status by inputting high level to the ATSK pin (Pin 85). When the serial data is $1, vibration detection can be monitored from the SENS pin. TE Anti Shock Filter TRK Gain Up Filter TRK Gain Normal Filter TRK PWM Gen ATSK SENS Comparator 85 80 Fig. 3-14. – 76 – CXD2545Q §3-11. Brake Circuit Immediately after a track jump of a certain size or more, the actuator setting worsens and it becomes difficult to return the servo suddenly to the on status. The brake circuit prevents these types of phenomenon from occurring. In principle, this circuit cuts unnecessary portions of the tracking drive and applies the brake by utilizing the 180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator cuts across the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 3-15 and 3-16.) Specifically, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 3-17.) TRK DRV FWD JMP REV JMP Servo ON RF Trace MIRR TE 0 0 TZC Edge TRKCNCL TRK DRV SENS TZC out Inner track outer track TRK DRV REV JMP FWD JMP Servo ON RF Trace MIRR TE 0 0 TZC Edge TRKCNCL TRK DRV SENS TZC out Outer track inner track Fig. 3-15. Fig. 3-16. 1 0 ∗ ∗ 0 ∗ ∗ ∗ ∗ 1 ∗ ∗ ∗ 0 ∗ ∗ ∗ ∗ 0 ∗ ∗ ∗ 1 ∗ ∗ ∗ ∗ 1 ∗ ∗ ∗ 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 0 0 0 1 TRACKING CONTROL 1 Fig. 3-17. ∗ : Don’t care Register name Command D23 to D20 D19 to D16 – 77 – CXD2545Q §3-12. COUT Signal The COUT signal is output in order to count the number of tracks passed over during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. However, the used TZC signal can be selected and there are two types of output methods according to the COUT signal application. 1-track jumps, etc. Fast phase COUT signal generation is performed using a fast phase TZC signal. High-speed traverse During high-speed traverse, reliable COUT signal generation is performed using a delayed phase TZC signal. This is because some time is required to generate the MIRR signal, and it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D16 when D19 = D18 = 1 and D17 = 0 are set with $3. (when D16 = 1, for delayed phase and high-speed traverse). In addition, the TZC signal delay can be selected from two values with D14 of $36. §3-13. Serial Readout Circuit The following measurement and adjustment results which have been specified in advance can be read out from the SENS pin (Pin 80) by inputting the readout clock to the SCLK pin (Pin 83) using serial command $39. (See Fig. 3-18, Table 3-19 and the Description of SENS Signals.) Specified commands $390C: VC AVRG measurement result $3908: FE AVRG measurement result $3904: TE AVRG measurement result $391F: RF AVRG measurement result $3953: FCS AGCNTL coefficient result $3963: TRK AGCNTL coefficient result $391C: TRVSC adjustment result $391D: FBIAS register value ••• ••• tDLS tSPW 1/fSCLK MSB LSB XLAT SCLK Serial Read Out Data (SENS) Item Symbol Min. Typ. Max. Unit SCLK frequency SCLK pulse width Delay time fSCLK tSPW tDLS 500 15 1 MHz ns µs Table 3-19. During readout, the upper 8 bits of the serial data must be 39 (Hex). Fig. 3-18. – 78 – CXD2545Q §3-14. Writing the Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40µs after the XRST pin (Pin 81) rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. §3-15. PWM Output FCS, TRK and SLD outputs are output as PWM waveforms. In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper. Timing Chart 3-20 and Figs. 3-21 and 3-22 show examples of output waveforms and drive circuits. The ON signal (FON and RON) is active low. tMCK = ≈ 180ns Timing Chart 3-20. 64tMCK 64tMCK 64tMCK AtMCK 1tMCK AtMCK SFON SFDR SRON SRDR SLD 32tMCK 32tMCK 32tMCK 32tMCK 32tMCK 32tMCK 1tMCK 1tMCK 1tMCK 1tMCK FFON/ TFON FCS/TRK FFDR/ TFDR FRON/ TRON FRDR/ TRDR Output value + A Output value – A Output value 0 1tMCK tMCK A 2 tMCK A 2 tMCK A 2 tMCK A 2 MCK (5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 5.6448MHz – 79 – CXD2545Q Example of Driver Circuits FON RDR RON FDR DRV – DRV + GND VDD Fig. 3-21. PWM Bridge Drive Circuit RDR FDR 22k 22k 22k 22k DRV VCC VEE Fig. 3-22. Operational Amplifier Drive Circuit – 80 – CXD2545Q §3-16. DIRC Input Pin The $2 command register can be changed by operating the DIRC input pin (Pin 82). Using the DIRC pin allows serial data transfer to be simplified during TRKJMP. Fig. 3-23 shows $2 command register changes produced by DIRC pin changes. In addition, Timing Chart 3-24 shows DIRC-based operations during TRKJMP. High level must be input to the DIRC pin when the XRST pin rises from low to high. Q3 0 0 1 1 Q2 0 1 0 1 Servo status OFF ON FWD JMP REV JMP Q3 1 1 1 1 Q2 1 0 1 0 Servo status REV JMP FWD JMP REV JMP FWD JMP Q3 0 0 0 0 Q2 1 1 1 1 Servo status ON ON ON ON Q1 0 0 1 1 Q0 0 1 0 1 Servo status OFF ON FWD MOV REV MOV Q1 0 0 1 1 Q0 0 1 0 1 Servo status OFF ON FWD MOV REV MOV Q1 0 0 1 1 Q0 1 1 0 1 Servo status ON ON FWD MOV REV MOV DIRC TRK SLD Q3, Q2, Q1 and Q0 correspond to D19, D18, D17 and D16 of $2. Fig. 3-23. $28 latch ON OFF OFF ON ON OFF ON OFF $2C latch XLAT DIRC FWD JUMP REV JUMP TRK SERVO SLD SERVO Timing Chart 3-24. – 81 – CXD2545Q §3-17. Servo Status Changes Produced by the LOCK Signal When the LOCK signal becomes low, the TRK servo assumes the gain-up status and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. – 82 – CXD2545Q §3-18. Description of Commands and Data Sets The following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. Input conversion converts these voltages into the voltages entering input pins before A/D conversion. Output conversion converts PWM output values into analog voltage values. Both types of conversion are calculated at VDD = 5.0V. If this voltage changes, the conversion values also change proportionally. (Voltage conversion = VDDX/5; VDDX: used supply voltage) $34 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 When D15 = 0. KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 — When D15 = D14 = D13 = D12 = 1. ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; FB9 is MSB two's complement data. For FE input conversion, FB9 to FB1 = 011111111 corresponds to +1V and FB9 to FB1 = 100000000 to –1V respectively. (when the supply voltage = 5V) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0 When D15 = D14 = D13 = D12 = 1. ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; TV9 is MSB two's complement data. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to +1V and TV9 to TV0 = 1100000000 to –1V respectively. (when the supply voltage = 5V) Note) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit of TV8 to TV0 during external write are read out. • When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. – 83 – CXD2545Q $35 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (3.36V/s) Focus drive output conversion FT1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 6.73 V/s 3.36 2.24 1.68 8.97 5.38 4.49 3.85 FT0 FTZ Focus search speed FS5 to FS0: Focus search limit voltage Default value: 011000 (±1.875V) Focus drive output conversion FG6 to FG0:AGF convergence gain setting value Default value: 0101101 $36 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 0 TG6 TG5 TG4 TG3 TG2 TG1 TG0 DTZC: DTZC delay (8.5/4.25µs) Default value: 0 (4.25µs) TJ5 to TJ0: Track jump voltage Default value: 001110 (≈ ±1.09V) Tracking drive output conversion TG6 to TG0:AGT convergence gain setting value Default value: 0101110 – 84 – CXD2545Q $37 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (+250mV); FE input conversion FZSH 0 0 1 1 0 1 0 1 +500mV +250 +125 +62.5 FZSL Slice level SM5 to SM0: Sled move voltage Default value: 010000 (≈ ±1.25V) Sled drive output conversion AGS: AGCNTL self-stop on/off Default value: 1 (on) AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms) Default value: 0 (63ms) AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGF 0 (small) 1 (large) 63mV 125 125mV 250 AGGT 0 (small) 1 (large) FE/TE input conversion AGV1: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGV2: AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGHS: AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGHT: AGCNTL high sensitivity adjustment time (128/256ms) Default value: 0 (256ms) – 85 – CXD2545Q $38 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) AGF: Focus automatic gain adjustment (on/off) AGT: Tracking automatic gain adjustment (on/off) DFSW: Defect disable switch (on/off) Setting this switch to 1(on) disables the defect countermeasure circuit. LKSW: Lock switch (on/off) Setting this switch to 1 disables the sled free-running prevention circuit. TBLM: Traverse center measurement (on/off) TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. All commands are on when set to 1.